KM3NeT CLBv2

CLB Reset after configuration: Solution in Firmware: Use End Of Startup (EOS signal in primitive STARTUPE2) to trigger a timer that keeps system reset asserted for 8.2 us. This ensures proper reset after FPGA configuration 8,2 us counter expires System Rst System Clk (62.5 MHz) ~9 us PLL startup -> clock EOS ~300 ns low after configuration done

XST versus Precision Revised StMachine and TDC files Cause: usage of VHDL libraries std_logic_arith and std_logic_unsigned in combination with numeric_std. Std_logic_arith is an old Synopsys implementation and should not be used since it is a non standard IEEE library (as such XST and Precision both have their own implementations!) Don’t use “initial values” when defining Signals and Variables Now synthesis via XST and Precision give equal results!

Monitoring channel Implemented! stmachine (2) IPMUX TDC Ch-0 TTDC Hits-0 Ch-1 TAES TMCH Ch-2 Ch-3 Test Hits-30 Clr LM32 Set Busy LM32 DPRAM IRQ Latch on “timeslice_start” Clear on “timeslice_start” Start register transfer on “timeslice_start” timeslice_start Added two registers in StMachine: Monitor Memory Base Monitor Memory Words (length: 1-256 words of 32 bits)

Flow control Implemented state machine “Control Status” register containing: TDC, AES and MCH enables TDC, AES and MCH flushes Monitor busy (for LM32_2nd polling) Enable stops data forwarding at UDP packet boundaries Flush forces a clear of all pending data in the pipeline Both needed to facilitate a clean start and stop/pause.

Flow control on system level How to implement DAQ back pressure that ultimately will overflow the front-end FIFOs? Overflow will cause loss of bookkeeping! We can signal this but action should be taken at system level. Currently: we are studying issues with the LM32_2nd Slow control that is being blocked sometimes Solved? Yesterday => Rev 140917-00 (tagged in SVN since it is flashed for the CLB for DOM-1) …backup slides “IPMUX”

Channel synchronicity Studying channel synchronicity (TDC, AES and MCH) showed failures. Revise State Machine, TDC, AES and MCH front-ends. Ongoing …backup slides

UDP Test packets generator Implemented on the 4th IPMUX channel. Controllable via “UDP test packet control register”: Trigger (bit 0 OR DIP-Switch 0) Continuous mode (bit 1 OR DIP-Switch 1)

G-Board underway: 8 165 165 82

EMC and Temperature Test Reports Test reports have been made for the assembly of a CLBv2.2.1 and PBv2.3 in a mushroom Temperature: https://docs.google.com/a/km3net.de/file/d/0B6xQ9LNuU6S8TUQ4T3dVXzZ6SWM /edit https://isvn.ific.uv.es/repos/KM3NeT/CLBv2/trunk/fw/CLBv2_Design/clb/doc/Therm alPictures/CLBv2_2_1_Plus_PBv2_3_Plus_Mushroom/KM3NeT_ELEC_WD_2014_ 004_ThermalMeasurements_PBv2_3_CLBv2_2_1_Mushroom_PJ_Draft.docx EMC: https://docs.google.com/a/km3net.de/file/d/0B6xQ9LNuU6S8RlUxQmpYUWdQUD A/edit https://isvn.ific.uv.es/repos/KM3NeT/CLBv2/trunk/fw/CLBv2_Design/clb/doc/EMC_ Measurments/KM3NeT_ELEC_WD_2014_005_EMC_Measurements_PBv2_3_CLB v2_2_1_Mushroom_PJ_Draft.docx

Switch tests (Standard) WR switch needs Auto Negotiation on in order to get the link up. Switch specialist Tristan Seurink: Test one switch with one port used for TX and another port used for RX Auto Negotiation off at CLB LM32_WR and at Switch ports Packets successfully received at both ends. (ping!) 2 separate switch ports Data to CLB Data from CLB

Switch tests details Juniper (type) Arista (type?) Arista (7150-64) Did the job! Arista (type?) Not able to disable Auto Negotiation Arista (7150-64) Not able to unlock SFP identification. Need dummy 8/10B coded stream to get switch (Tx) port up (the Rx CDR has no lock and the port is signalled down) Data from CLB Data to CLB

Switch tests next steps Does this scheme work over multiple levels of switches? Try other switch vendors

Todo list Fix State Machine, TDC, AES and MCH (David, Antonio, me) Re-arrange MCH channel (proper time-tag; not lagging one time-slice => me) Flow-Control study: Fix Slow Control => thoroughly test yesterdays solution define system level actions when frontends overflow ICAPE2 / multiboot / watchdog / golden image tests Software: Communication interface between LM32_2nd and LM32_WR SFP readout and setting (loopback, PRBS, wavelength tuning) Auto negotiation control Ethernet flow control (received pause frame implementation in the CLB)

Backup slides

Data Channel Synchronicity TimeSlice_Start TimeSlices State Machine Enables TDC FIFO AES FIFO MCH Example: TDC has no data and thus no header is composed (state “waiting” since fifo is empty). Fifo gets non-empty at the first TimeSlice_Start; now a (yellow) header is composed. AES has data as soon as it is enabled. Therefore is starts to compose a (red) header (state “waiting” -> “header” when fifo non-empty) MCH only starts to compose a (yellow) packet when TimeSlice_Start is asserted

Data Channel Synchronicity TimeSlice_Start TimeSlices State Machine Enables TDC FIFO AES FIFO MCH Example: TDC and AES have data as soon as they are enabled. Therefore they start to compose a (red) header (state “waiting” -> “header” when fifo non-empty) MCH only starts to compose a (yellow) packet when TimeSlice_Start is asserted

IPMUX Anyone has data? Priority! Stream Selector Anyone has data? TDC FIFO 512 EOD UDP Packet Buffer AES FIFO 512 1) Header will be transferred first, tail of packet is underway 2) IPMUX Stream selector locks on TDC stream, transfers header and waits… 3) Until End Of payload Data (EOD) marker is passed (at the end of a time-slice) MCH FIFO 512 FIFO 512 Priority! Lm32_2nd If time slices are chosen to be “long” (1 second) then IPMUX channels keeps lock on the selected stream for that amount of time. Even the high priority of the LM32 doesn’t help now! Funny, but with high rates each stream is served as expected!

IPMUX-2 Anyone has data? Priority! Increase size of input FIFOs… Stream Selector Anyone has data? TDC FIFO 8192 EOD UDP Packet Buffer AES FIFO 8192 No matter the size of the FIFO the problem persists MCH FIFO 8192 FIFO 8192 Priority! Lm32_2nd Increase size of input FIFOs… This does solve the key problem but it reliefs other input channels from “full” situations. More is needed…

Anyone has a complete packet to transfer? IPMUX-3 Stream Selector Anyone has a complete packet to transfer? TDC FIFO 8192 EOD EOD EOD FIFO 8192 UDP Packet Buffer AES 1) Since “data” FIFO can now hold at least one packet… 2) …We can keep track of any packet tails (EOD) present in a parallel “EOD” FIFO (you actually only need the FIFO flag structure, no need to store any data!) 3) Now the Stream selector only initiates an action when a complete packet can be transferred FIFO 8192 FIFO 8192 MCH FIFO 8192 FIFO 8192 FIFO 8192 FIFO 8192 Priority! Lm32_2nd