Lecturer: Dr. Samuel Kosolapov ksamuel@braude.ac.il Theory of Analog Electronics FET Part 3. FET as Amplifier * In this presentation definitions and examples from Wikipedia, HowStaffWorks and some other sources were used ORT Braude Engineering College. Course: Theory of Analog Electronics 31401. Lecturer: Dr. Samuel Kosolapov ksamuel@braude.ac.il

Quiz 07. 3 (before the start): Do You need this lecture ? May be most of the students already knows “the material” “Handasaim”, please do not answer. Goal of the quiz (to be automated some day): To get an instant feedback

Items to be defined/refreshed/discussed Steps in FET Amplifier Design Q-Point (DC Analysis) (by using equations) Develop small-signal AC Model about Q-point Voltage Gain Calculations

Goals Design Practical FET amplifier Propose numerical values of the elements of the amplifier (VDD, resistors, etc) Evaluate/Calculate parameters of the amplifier (Gain, RINPUT, ROUTPUT, etc) Evaluate limitations of the chosen design

Steps (In the real life) 1. Propose circuit (something like Vacuum Triode amplifier) 2. Select Q-point and circuit components values 2a) Using graphical analysis 2b) Using analytic expressions (possible with FET) 3. Develop small-signal model of the FET about Q point. (using real characteristics or FET data provided by manufacturer) 4. Replace FET to its small-signal model 5. Compose node’s equations for small AC signal. 6. Solve node’s equations (and thus get Gain, RINPUT, ROUTPUT, etc) 7. Analyze solution (very important step) 8. Improve design. 9. Goto 2. 10. Send design to tests and to the production line (get money)

Steps (For Exam) 1. Find circuit to analyze (Provided by lecturer on Fig X.1) 2. In accordance with Page 1 of the exam: Claim that FET is in the “active region” (Constant current region) (FET on analog electronic exams is always in active region, othervise this exam is about digital electronics ) 3. Replace FET to its small signal model (provided by teacher on Fig X.2) 4. Compose node’s equations for small AC signal. 5. Solve equations and generate answer to the questions. 6. Option: analyze results and provide self-test 7. Get grade The same steps will be valid for electronics amplifier of any type, but for JFET graphs, equations and solutions are relatively simple.

Steps 2b-1, 2. Select Q-Point: VGS(Q), ID(Q) Without Graphs !!!

Step 2a-4. Calculate ID(Q), Evaluate RS VGS(Q)=VGS(off)/2 = -2V;

Step 2a-5. Select VDD and VDS(Q) and Calculate RD Without Graphs !!!

Step 3-1. Develop small-signal AC model for the FET about Q-point Important FET parameter

Step 3-1. Develop small-signal AC model for the FET about Q-point; Numerical Value of gm

Step 3-2. Simplest Small-signal AC model for the FET Finally: we have ideal current source DID regulated by voltage DVGS This approximation is ACCURATE for small changes of VGS only  SMALL-SIGNAL TECHNIQUE.   Electronic Equivalent of the FET for SMALL-SIGNAL is: (explain again and again until … )

Step 3-3. Practical Small-signal AC model for the FET FET AC Model parameters: (typical values) Rgs is very large ~ 109 W ( ~1012 W for MOSFET )   Rds ~ 50kW  Gm ~ 0.01S Some manufacturers provide small-signal parameters. It is possible to get those parameters (except Rgs) from FET characteristics EXTREMELY IMPORTANT:

Step 3-4. Evaluation gm from Characteristics

Step 3-5. Evaluation of RDS from Characteristics VGS(Q) =-2V Work (Quiescent) Point: VGS(Q) = -2V VDS(Q) = 10V ID(Q)=2.5 mA {20V, 0mA}

Step 4. Replace FET for its small-signal AC model Idea: FET is in the active (constant) region. (if not all the rest is invalid) Then , in case input signal is SMALL AC signal, FET may be replaced to its SMALL-SIGNAL model

Step 4-1 Draw FET small-signal AC model in the center of the blank page

Step 4-2 Add all circuit components

Step 4-3 Use Superposition and “Simplifications” Shorten “Power Supply Battery” AC Analysis !!!

Step 4-4 Circuit ready for AC Voltage Node Analysis Better presentation (not a must) Explain Name: “Common Source”

Step 5 Compose AC Voltage Node Analysis

Step 6 Solve AC Voltage Node Analysis (To get Voltage Gain) Solution is extremely simple in this case (because of “simplifications”)

Step 6-1 Simplify Solution Practically, life is much simpler:

Step 6-2 Find RINPUT and ROUTPUT No need to make long calculations:   RINPUT = RG || RGS ~ RG  RINPUT is HUGE: up to 1012W !!!!!!!! ROUTPUT = RDS || RD ~ RD ~ 3 kW : BAD !!!! 

Step 7. Analyze Solution (Very important step)

Step 7. Analyze Solution (Static and Dynamic Work Line) VDS is changing not according to “GREEN” WORK LINE (Static Work Line, slope is according to 1/(RD+RS) ) But ACCORDING TO RED WORK LINE (Dynamic Work Line, slope is according to 1 / (RD||Rload ) )  AC Voltage Gain < 9 VGS(Q) =-2V Q-Point

Step 8. Improve Design Av ~ Gm*RD We want MORE GAIN: Option 1: Increase Gm Option 2: Increase RD

Step 8-1. Improve Design: Increase Gm (By selecting another Q-Point) Q1: {VGS(Q) ~ -1 V} gm = Slope of the derivative “Old “Q-Point” Gm was ~ 2.5 mS Q: Gm increased, but what about Voltage Span ?

Step 8-2. Improve Design: Increase Rd VGS(Q) =-2V New Q-Point VGS(Q) =-1V Old Q-Point Example: RD = 10kW: Voltage Gain is 3.75*10 ~ 40  Better Problem ! VDD must be increased to enable this. But then, what about Power dissipated on FET (P = I*V) ??? What are “small-signal” limits ?

Reminder: Steps (In the real life) 1. Propose circuit (something like Vacuum Triode amplifier) 2. Select Q-point and circuit components values 2a) Using graphical analysis 2b) Using analytic expressions (possible with FET) 3. Develop small-signal model of the FET about Q point. (using real characteristics or FET data provided by manufacturer) 4. Replace FET to its small-signal model 5. Compose node’s equations for small AC signal. 6. Solve node’s equations (and thus get Gain, RINPUT, ROUTPUT, etc) 7. Analyze solution (very important step) 8. Improve design. 9. Goto 2. 10. Send design to tests and to the production line (get money)

Reminder: Steps (For Exam) 1. Find circuit to analyze (Provided by lecturer on Fig X.1) 2. In accordance with Page 1 of the exam: Claim that FET is in the “active region” (Constant current region) (FET on analog electronic exams is always in active region, othervise this exam is about digital electronics ) 3. Replace FET to its small signal model (provided by teacher on Fig X.2) 4. Compose node’s equations for small AC signal. 5. Solve equations and generate answer to the questions. 6. Option: analyze results and provide self-test 7. Get grade The same steps will be valid for electronics amplifier of any type, but for JFET graphs, equations and solutions are relatively simple.

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