BaBar Silicon Tracker Perspective at High Luminosity G. Calderini

Which will be the performance of the BaBar SVT when the lumi increases? Main issues: radiation damage, occupancy Performance of the present SVT with minor modifications: (Short term perspective: n x 1034) Strategy to cope with future physics programs: (Long term perspective: n x 1035 to 1036)

Present detector: Short Term extrapolation Extrapolation for the short term is based on expectations for currents Step 1 Currents are used to calculate instantaneous dose rates, by using background studies

Instantaneous dose Step 2 Integrated dose Occupancy (radiation damage) (performance) B.Petersen G.Rizzo, G.C.

Occupancy (performance) Step 3 extrapolated hit efficiency extrapolated hit resolution M.Mazur M.Mazur

The 1035 scenario The 1036 scenario Extrapolations suggest that a detector like it is now, can work well up to a 2-4 x 1034 Which are the limits imposed to the tracker by more aggressive physics programs? The 1035 scenario The 1036 scenario

present similar concerns: The (1-2) x 1035 and 1036 scenarios present similar concerns: Machine-related background (continuous injection!) Radiation damage Rate Physics backgrounds But they are completely different worlds

In a 1035 world, a BaBar-like tracker with SVT-DCH is somehow possible More phase-space for solutions! In a 1036 world, life is different, more effort necessary in the design 7MRad/y 100% Occupancy SVT DCH

Vertexing and Tracking at high luminosity The beam-pipe The beam-pipe radius is a big issue, the choice may depend strongly on the machine design KEK-B plans on 1cm  more performing PEP-II plans on 1.5-2 cm  safer The inner tracker One or two layers of pixels very close to beam-pipe mainly required for background suppression, integrated by a few additional layers of silicon strip detectors (vertexing, impact parameter resolution, low-P tracking) The central tracker: two options a) More silicon layers b) Small cell/fast gas drift chamber, combined with normal drift chamber

Some keypoints Radiation hardness: possible using LHC technology Material budget: current hybrid pixel layers are thick; the all-silicon solution can get pretty heavy Rate capability: effects on silicon segmentation and drift chamber cell size

Babar possible approach to tracking All silicon tracker, with lampshade shaped modules to reduce material Start to explore different options Main issue is material Need R&D on thin DSSD and pixels Pixel (2 layers) Intermediate DSSD (3 layers) Central Silicon Tracker(4 layers) R(outer) = 60 cm

Pixels (I) A) Hybrid pixels In hybrid pixel systems the readout chip is connected to the sensor through solder or Indium bumps Separate development of readout electronics and sensors Use best available technology for each component Front-End Chip Sensor Complexity and reliability issues in assembly Material budget is high due to overlap of sensor and readout chip.

Example: Pixels at LHC LHC experiments use hybrid pixels Radiation hardness and rate capability are high They should be OK for a Super B-factory as well. Material budget is serious: At least 1-2% X0 per layer (current Babar Si is around 0.4% X0) Overlap of: Sensor Front-end chip Flex hybrid with control chip, caps Mechanical structure and cooling Atlas pixel modules

What dominates resolution? Here material budget is critical ! What dominates resolution? s(point)2 = s(mult.scatt.)2 + s(detector)2 Typical SVT detector resolution at BaBar is s = 12 - 14 mm at 90° For p=1 GeV/c, for R=3 cm, X(beampipe+1st layer) = 1.4% X0 s(mult. scatt.) = 50 mm at 90° Impact parameter resolution is dominated by resolution on first hit

Model for resolution We can model the SVT performance using a resolution-weighted average of the detector radii. F.Forti Data 1 GeV58mm 3 GeV25mm 1 GeV55mm 3 GeV23mm

Where can we gain ? We could gain a lot by reducing the beam pipe radius and the detector + beam pipe thickness. The point resolution can be improved 1 GeV12mm 3 GeV7 mm F.Forti

Pixels (II) B) Monolithic Active Pixels (MAPS) Possible approaches: Sensor and electronics on the same substrate. Possible approaches: Integrate electronics on the high resistivity substrate usually employed for sensors Active components are not of the best quality The fabrication process is highly non-standard with large feature size (>1-2 mm) Signal is high quality, and large Use the low resistivity substrate of standard CMOS process as sensor Standard sub-micron process with state-of-the-art electronics Proven by the success of CMOS video cameras, replacing CCDs. Small signal due to the collection mechanism

CMOS MAPS Use epitaxial layer of CMOS low-resistivity substrate to collect charge (thermal diffusion) Potential for low cost and very small thickness (reduced substrate). Radiation hard if using sub-micron CMOS process Low power-consumption (circuitry active only during read-out) Until now: miniscule pixel size (a few um) prevents usage in large system

Pixel: ongoing R&D Conventional hybrid pixels MAPS Reduce thickness It doesn’t seem possible to reduce too much preserving also the mechanical stability MAPS Develop large-area detectors (already some results) Development on-going in several places: LEPSI, LBNL, Japan, Perugia Project launched by Pisa-Pavia-Bergamo-Trento-Trieste-Modena to the Italian Ministry for Education and Scientific Research - Main goal is to develop a submicron CMOS MAPS that can be used on large area systems - Time frame is 2-3 years

Strips 1) Reduce the thickness of the active silicon In the central silicon tracker momentum resolution dominated by material budget 1) Reduce the thickness of the active silicon Signal reduction (1 MIP ˜ 8000 e/100um Si) Mechanical issues: silicon greatly contributes to module stiffness 2) Reduce the amount of inactive material Bring the signal out of the active tracking volume Done already for the present SVT

The same technique cannot be used in the larger volume Central Silicon Tracker Need some local signal amplification Reduce thickness of readout electronics For the chip themselves is mainly a mechanical problem, could be solved. It is harder to do for the hybrids (capacitors, traces, etc.,) Reduce power dissipation (ie cooling) Very hard if one has to improve the S/N ratio to be able to readout smaller signals One more reason to go for sub-micron process

All-silicon performance Momentum resolution at low-p is dominated by multiple scattering in silicon material To keep a reasonable performance we need 100um thick silicon, which isn’t quite ready yet: R&D on thin silicon modules On this large area it will be impossible to keep all the electronics outside the active volume R&D on thin, low power electronics How much the requirement on momentum resolution at low momentum can be relaxed ? More physics studies s(1/pt) (GeV-1) Current DCH Double-sided strip @ 100um

Summary and conclusions Pixel layers Current LHC pixel would work, but too much material. Develop monolithic pixels Large structures, thickness (back-thinning), radiation damage Central tracker Most likely it won’t be possible to achieve the same performance of current systems at low momentum It would require a <100um equivalent thickness for a 9 layers (total) all Si tracker. Explore the possibility of gaseous detectors, such as a small-cell DCH. Some R&D has started, but we need to proceed fast if we want to design a realistic system in 2-3 years.