Design Entry: Schematic Capture and VHDL ENG241: Digital Design Week #4

References Kenneth Sort, “VHDL For Engineers”, Prentice Hall, 2009. Peter Ashenden, “The designer’s guide to VHDL, 2nd edition”, Morgan Kaufmann publishers, 2002. Douglas Perry, “VHDL”, 3rd Edition, McGraw Hill. Sudhakar Yalamanchili, “Introductory VHDL: From Simulation to Synthesis”, Prentice Hall, 2001. Sudhakar Yalamnachili, “VHDL: A Starter’s Guide”, 2nd Edition, Prentice Hall, 2005.

Design Entry Schematic capture Hardware Description Language (HDL) What you already did in previous labs. Hardware Description Language (HDL) VHDL Verilog Electronic System Level (ESL) Higher level possible – C-like and Java-like ImpulseC, HandelC, Catapult C, Vivado HLS

Schematic Design

What is HDL? Hardware Description Languages (HDLs) are languages used to document (model), Communicate design, simulate, and synthesize digital circuits and systems.

VHDL: Introduction VHDL is an acronym for “VHSIC Hardware Description Language”. VHSIC is an acronym for “Very High Speed Integrated Circuits” program. It was a US government sponsored program that was responsible for developing a standard HDL. VHDL supports modeling and simulation of digital systems at various levels of design abstraction.

Basic Modeling Concepts External Interface circuit Internal Functionality A E B Outputs Inputs

Basic Modeling Concepts

Basic Modeling Concepts External Interface modeled by “entity” VHDL construct. Entity name Port name entity ckt1 is port (X,Y,Z : in bit; F : out bit); end entity ckt1; Port Port mode VHDL “port” construct models data input/output.

Basic Modeling Concepts Internal Functionality modeled by “architecture” VHDL construct Entity name Architecture name architecture behav of ckt1 is begin F <= X or (not Y and Z); end architecture behav;

Lexical Elements Comments: Identifiers: - A comment line in VHDL is represented by two successive dashes “- -”. A comment extends from “- -” to the end of the line. Identifiers: Identifiers are names that can be given by the user. rules: >> must start with an alphabetic letter. >> can contain alphabetic letters, decimal digits and underline character “_”. >> cannot end with “_”. >> cannot contain successive “_”.

Legal vs. Illegal Identifiers Valid identifiers A, X0, counter, Next_Value Invalid identifiers last@value  contains illegal character 5bit_coutner  starts with nonalphabetic _A0  starts with an underline A0_  ends with underline clock__pulses  two successive underlines

Libraries A library refers to a collection of declarations (type, entity, sub-program) and their implementations (architecture, sub-program body). The actual specification of a library varies from one simulation package to another. In VHDL we usually use the IEEE library and have to declare that at the beginning of our VHDL program.

Library: Example For standard logic (std_logic) the basic package is ieee.std_logic_1164. This package defines the values and basic logic operators for type std_logic. The declarations can be made visible in our model file by : library IEEE; Use IEEE.STD_LOGIC_1164.ALL; Library Package

std_logic type Demystified Value Meaning ‘U’ Not Initialized ‘X’ Forcing (Strong driven) Unknown ‘0’ Forcing (Strong driven) 0 ‘1’ Forcing (Strong driven) 1 ‘Z’ High Impedance ‘W’ Weak (Weakly driven) Unknown ‘L’ Weak (Weakly driven) 0. Models a pull down. ‘H’ Weak (Weakly driven) 1. Models a pull up. ‘-’ Don't Care Signals are used to connect different parts of a design. They can be thought of as “wire” in conventional sense. Every signal has a type. Signals are used to connect different parts of a design. They can be thought of as “wire” in conventional sense. Every signal has a type. A type is all the valid values that a signal can assume. VHDL naturally supports bit type, which allows signals of this (bit) type to take the values ‘0’ or ‘1’. Signals of type integer can take integer values between +(231 – 1) to -(231-1). Wire in real implementation may need to take an unknown value, ‘X’ or high impedance value, ‘Z’. Thus, IEEE 1164 standard defined std_logic with nine values listed in Table 1. Std_logic_vector is an array or vector of std_logic type. It represents a bus and has dimension associated with it, which is known as the range of vector.

Complete Program -- Library Declaration Library IEEE; Use IEEE.std_logic_1164; -- Entity Declaration Entity ckt1 is Port (X,Y,Z : in std_logic; F : out std_logic); end ckt1; -- Architecture Declaration architecture behav of ckt1 is begin F <= X or not Y and Z; end architecture behav;

VHDL Design Styles VHDL Design Styles dataflow behavioral (algorithmic) structural Concurrent statements Components and interconnects Sequential statements Registers State machines Test benches Subset most suitable for synthesis ENG241/Digital Design

Example: Concurrent Statements This circuit could be modelled as following: f <= z or w; z <= x and y; x <= not a; w <= a and b; y <= not b; ENG241/VHDL Tutorial

Bit type Bit is also a predefined enumerated type Operations Logical: =, /=, <, >, <=, >= Boolean: and, or, nand, nor, xor, xnor, not Shift: sll, srl, sla, sra, rol, ror

Mapping the Design onto Digilent FPGA Board Netlist -- Library Declaration Library IEEE; Use IEEE.std_logic_1164; -- Entity Declaration Entity ckt1 is Port (X,Y,Z : in std_logic; F : out std_logic); end ckt1; -- Architecture Declaration architecture behav of ckt1 is begin F <= X or not Y and Z; end architecture behav; Synthesis Map, Place and Route Generate Bitstream Download 000111010100000000011111001010101010000010100101010101010001100101010110011000