First production of Ultra-Fast Silicon Detectors at FBK 14th Topical Seminar on Innovative Particle and Radiation Detectors 
(IPRD16) 3 - 6 October 2016   Siena, Italy First production of Ultra-Fast Silicon Detectors at FBK Giovanni Paternoster On behalf of UFSD Collaboration INFN Torino, Univ. Torino, Univ. Trento, TIFPA, FBK, UCSC Santa Cruz

Summary Ultra Fast Silicon Detectors: Aims and Motivations UFSD technology at FBK First Production of UFSD at FBK Parametric and Functional Characterization: 4.1 I-V 4.2 Gain 4.3 Effect of Temperature 4.4 Timing Conclusions and next activities

Ultra Fast Silicon Detectors Physics Aim: developing a radiation detectors featuring Ultra Fast timing resolution: ≈ 10 ps High spatial resolution: ≈ 10’s of µm + - UFSD: a silicon detector that looks like a normal pixel or strip sensor, but with a much larger signal Based on LGAD (Low Gain Avalanche Detectors) technology featuring low gain (5-20) Advantages: High signals also with thin silicon substrates Better timing performance Easy to be segmented Low gain -> low excess noise

UFSD technology In order to reach the Ecrit value (~3x105 V/cm) with a standard n+-p junction a Bias of thousands of Volts should be applied (not possible!!) n++ P-stop Gain Layer P+ N-deep Including a p-doped enriched region close to the surface n++-p-in-p+ structure High-Field region: Electric Field > 2e5 to activate the impact ionizing multiplication Junction Termination & Guard Ring: controls the Electric Field at the border region

Design of the Gain Layer 1. Shallow implant + diffusion The doping profile of the Gain layer controls the shape of the Electric Field 2 technological approaches are possible: Doping Profiles Boron Phos. 2. Deep Implant Phos. Boron The deep implant approach has several advantages: Avoid peaked Electric Field -> less noise Is more reliable (independent of thermal diffusion and of doping compensation effect)

Optimization of the Gain layer The Gain Layer doping profile has been finely tuned to reach the target Gain and high Breakdown Voltage VBD vs Doping Gain vs Doping 1 1.04 1.08 1.12 Normalized Gain Layer Dose = 1.08 Gain Gain Layer Dose = 1.04 Bias Voltage (Volts) Both the Gain and the Breakdown Voltage are very sensitive to the doping level of the gain layer! G.F. Dalla Betta et al. “Design and TCAD simulation of double-sided pixelated low gain avalanche detectors”, NIMA 2015

UFSD technology Edge termination High-field region Goal: design an edge termination structure able to support VBD > 1000V after irradiation! 12 rings Guard-ring structure supporting n-deep and p-stop rings Radiation damage is taken into account (NOX = 1e12) in simulations Simulated Breakdown = 1270 Volts After irradiation!

Detector Design Segmentation Electrode segmentation makes the E field very non uniform, and therefore ruins the gain and timing properties of the sensor

UFSD Design: Segmentation Three different approaches for device segmentation have been investigated 1. N-side segmentation: both n+ and the gain layers are segmented (some concerns about E field uniformity) 2. P-side segmentation: the p layer opposite to the gain layer is segmented (the signal from holes is read -> worse timing) 3. AC coupling: The signal is frozen on the resistive sheet, and it’s AC coupled to the electronics

First UFSD production at FBK

UFSD Characterization I-V curves Gain Split 3 Gain Split 1 Gain Split 2 No Gain The Breakdown Voltage decreases by increasing the gain layer doping The foot at low voltage indicates the indicates the depletion of the gain layer. Simulated BD: Split 1: 1100 Volts Split 2: 880 Volts Split 3: 500 Volts M. Ferrero presented at 28th RD50 Workshop, 2015

UFSD Characterization: GAIN Gain vs Bias Voltage for detectors with different gain Gain Split 3 Gain Split 2 Gain Split 1 Gain measured with a laboratory setup by using a laser at 1064 nm Measured Simulated Good agreement between simulated and measured Gain.

Characterization vs Temperature Gain Split 2 decreasing of the leakage current in the sensor (thermal noise) 25 °C 20 °C 15 °C 10 °C Current vs Bias Voltage at different temperatures The impact ionization rates vary greatly with temperature leading to an increase of the gain Gain Split 2 25 °C 20 °C 15 °C Bias Voltage Gain vs Bias Voltage at different temperatures The study of the temperature dependence on the sensor performance is crucial for calibration in order to operate at very low temperatures, as requested by some of the major experiments. GAIN Bias Voltage Bias Voltage

UFSD Characterization: Timing Gain Split 3 Gain Split 2 Gain Split 1 Time Resolution vs Bias voltage Gain Split1: σt(@800V ) ≃ 300ps Gain Split2: σt(@800V ) ≃ 90ps Gain Split3: σt(@550V ) ≃ 55ps Gain Split 2 25 °C Time Resolution vs Bias voltage 20 °C 15 °C Very good timing performance obtained with the two splits with higher gain (considering a 300 µm thick substrate!) Time Resol. (ps) Bias Voltage (Volts)

Next Activities How to further improve the timing resolution? The slew rate: Increases with gain Increases ~ 1/thickness Improvements in timing resolution requires thinner detectors! N. Cartiglia presented at AIDA 2020 annual meeting, Hamburg 2016

Next Activities A new production batch on 60 µm thick substrates will start soon in FBK Low-resistivity handle wafer 60 µm High-resistivity silicon wafer 570 µm 60 µm active thickness Single side process N+ segmentation Single pads, pixel arrays and strips

Next Activities Some simulation results on next 60µm thick UFSD Tuning of the Gain layer Dose!! With respect to the 275µm devices both the Breakdown and the Operational Voltages are much lower Gain as a function of the interaction position: For N+ side Segmented detectors the gain falls to zero at the detector borders and is almost constant in the detector core region!! GAIN Guard ring detector N. Cartiglia: INFN Torino X position

Conclusions A new microfabrication technology for production of UFSD has been developed at FBK The first batch resulted in working devices featuring low noise. The first fabricated batch showed very promising results in terms of : Breakdown Voltage: 500-1000 Volts (depending on the gain split) Gain value in the range of 5-40 Excellent timing resolution In order to further improve the timing resolution of the devices a new batch based on 60 µm thick substrate is going to be produced.

INFN Torino, Univ. Torino, Univ. Trento, TIFPA, FBK, UCSC Santa Cruz Thank you for your attention! UFSD Collaboration INFN Torino, Univ. Torino, Univ. Trento, TIFPA, FBK, UCSC Santa Cruz Acknowledgements: " Part of this work has been financed by the European Union’s Horizon 2020 Research and Innovation funding program, under Grant Agreement no. 654168 (AIDA-2020) and Grant Agreement no. 669529 (ERC UFSD669529), and by the Italian Ministero degli Affari Esteri and INFN Gruppo V." In future HEP experiments like upgrade of the Compact Muon Solenoid experiment (CMS) at the Large Hadron Collider (LHC), CERN and the proposed International Linear Collider (ILC), the Si tracking detectors will be operated in a very harsh radiation environment, which leads to both surface and bulk damage in Si detectors which in turn changes their electrical properties, i.e. change in the full depletion voltage,

Next Activities Some simulation results on next 60µm thick UFSD Tuning of the Gain layer Dose!! With respect to the 275µm devices both the Breakdown and the Operational Voltages are much lower Gain as a function of the interaction position: For N+ side Segmented detectors the gain falls to zero at the detector borders and is almost constant in the detector core region!! GAIN Guard ring detector N. Cartiglia: INFN Torino X position