Introduction to Mixed-Signal, Embedded Systems Design Alex Doboli, Ph.D. Department of Electrical and Computer Engineering State University of New York at Stony Brook Email: adoboli@ece.sunysb.edu ©Alex Doboli 2006

An Overview on the Design of Embedded Mixed-Signal Systems The chapter introduces embedded mixed-signal systems and explains the top-down design flow for developing performance efficient implementations Types of embedded applications and their characteristics (interfaces, functionality, and design requirements) CPUs used in embedded systems (microprocessors and microcontrollers, DSP, VLIW processors, and reconfigurable architectures) Top-down design flow based on design refinement and circuit modeling The evolution of the embedded systems market Illustrating example for a embedded mixed-signal system design ©Alex Doboli 2006

Sensing and actuation devices in embedded applications ©Alex Doboli 2006

Embedded Applications Signal sensing/data acquisition – data processing & data storing – actuation – data communication (networking) ©Alex Doboli 2006

Embedded Applications Networking, intelligent control ©Alex Doboli 2006

Embedded Applications Networking ©Alex Doboli 2006

Types of Embedded Applications (1) A. Embedded controllers Supervise and adjust the behavior of the monitored entities Fan controller, pacemakers, robot arm controller, Low/medium computational complexity, real-time, safety-critical, accurate sensing, low cost B. Specialized interfaces Interfacing to powerful computers Supply the missing hardware Relieves the computer from interfacing jobs: data conversion, encoding/decoding, encryption/decryption, etc. Small cost & size, low/medium computational complexity, fast throughput, low energy consumption Data acquisition, networking cards, capacitive sensing, mouse ©Alex Doboli 2006

Types of Embedded Applications (2) C. Application-specific coprocessors Customized data intensive processing: DSP, multimedia, graphic processors, image processing, video processing Relieves CPU from computationally intensive tasks High speed, low power consumption, low cost & size D. Networks of embedded systems Automotive applications: networked embedded microcontrollers, sensors, actuators Wireless networks, sensor networks Low cost, small size, reduced memory, low energy consumption, variety of sensors/actuators Communication protocols, data routing, data aggregation, control, scalability, self-organizing, autonomous ©Alex Doboli 2006

Data Flow in an Embedded System ©Alex Doboli 2006

Summary of Embedded Systems characteristics System types Sensing Actuation Data communic. Data processing Requirements & constraints Controllers Wide range - control Cost, accuracy, timing, safety Specialized interfaces Various speed Conversion,formatting,encoding Cost,size,accuracy,timing, power consumpt. Co-processors High-speed Data-intensive customized Cost, size, speed, power consumpt. Networks of embedded systems Control, conversion, encoding Cost, size, safety, power consumpt. ©Alex Doboli 2006

I/O Interfaces Analog and digital signals Voltage, current, charge, frequency, phase Thermistors, theromocuples, pressure sensors, velocity sensors, strain gauges, etc. Signal conditioning circuits, analog multiplexers, ADC, DAC, comparators, filters, sampling circuits, amplitude detectors, mixers, etc. Analog signals Sin waves, triangular, Range, bandwidth, precision, noise, speed of variation etc. ©Alex Doboli 2006

Functionality Control dominated systems Data dominated systems Multi tasking systems Multi-mode systems ©Alex Doboli 2006

Types of functionality ©Alex Doboli 2006

Types of functionality Continuous time systems Discrete-time systems Event-driven systems ©Alex Doboli 2006

Design requirements Low cost Short time to market Small size & weight Real-time constraints, latency, throughput Low power & low energy consumption Safety Data accuracy Robustness Flexibility in developing new applications ©Alex Doboli 2006

Timing (real-time) constraints ©Alex Doboli 2006

Analog Circuit Nonidealities ©Alex Doboli 2006

System performance & requirements Global constraints Local constraints Constraint transformation Tightly coupled systems Loosely coupled systems ©Alex Doboli 2006

Embedded vs. other applications (1) How do embedded applications differ from “non-embedded” ones (e.g., desktop)? A. Wide range of sensing & actuation necessities: The temperature sensor provides an output voltage proportional to the measured temperature The fan is a DC brushless fan with a duty cycle (hence speed) controlled by the output of the embedded controller The tachometer measures the rotational speed of the fan, and generates an input signal used by the embedded system for computing the fan speed => Knowledge required beyond EE & CE (physics, chemistry, mechanics, material science, etc.) ©Alex Doboli 2006

Embedded vs. other applications (2) B. Variety of design and performance requirements Cost Weight, size, number of I/O pins Latency, throughput, real-time constraints, response time, Energy/power consumption Safety-critical C. Comprehensive design process System design (beyond CPU) Analog and mixed-signal circuit design Customized digital circuit design Software development: algorithms, drivers, firmware, ISR, API => Cross-disciplinary design expertise (EE & CE & CS) ©Alex Doboli 2006

PSoC Mixed-Signal Architecture ©Alex Doboli 2006

Other Embedded Architectures Microcontrollers DSP Reconfigurable architectures ©Alex Doboli 2006

Tow-Down Design Flow (1) ©Alex Doboli 2006

Design Flow (2) Goal: customize the hardware and software according to the specific functional, cost, and performance needs of the application, as well as the characteristics of the environment the design will operate in Customization allows achieving the performance requirements at relatively low costs Customization leads to lesser flexibility in efficiently reusing an embedded system design for a different kind of application Customization involves cost-size-performance trade-offs ©Alex Doboli 2006

Design Flow (3) Abstract system specification Functional, interfacing, cost, and performance requirements of the system Incremental refinement during the top-down flow Adds successively implementation details to the design Early refinement steps decide the # of processing cores, partitioning of the functionality to the cores, the structure of the memory subsystem, the number of buses, etc. Late refinement steps implement the building blocks Each refinement step conducts design trade-off analysis Multiple solutions and impact on the system performance System performance evaluation Modeling procedure for the building blocks in the design ©Alex Doboli 2006

Design Flow (4) 1. System specification: Describing the interfacing, functionality, and performance constraints of an embedded system Simulatable notation SystemC, MATLAB/SIMULINK, UML, VHDL, VHDL-AMS @ different levels of abstractions High level vs. low level specifications 2. Functional partitioning: Re-organizes a specification into modules with specialized functionality The identified modules might undergo different design procedures Might be performed multiple times ©Alex Doboli 2006

Design Flow (5) 3. System-level trade-off analysis: Maps (transforms) system-level performance and design requirements into requirements for the building blocks Design trade-offs are analyzed during this step cost -speed, speed - power consumptions, etc. Whether a module is realized in hardware or software Deciding the main attributes of the memory memory size, # of memory modules, access time, etc. Number of I/O ports, their communication protocols, mapping of I/O signals to ports, etc. Refining the OS or firmware level routines Task scheduling, arbitration of module access to buses Modules are individually designed ©Alex Doboli 2006

Design Flow (6) 4. Design of the individual modules: Implementing the system modules Interfaces, video and audio processors, memory module, bus communication Hardware circuits Software routines Drivers, interrupt service routines (ISR), control and data access routines Complex modules go through top-down design ©Alex Doboli 2006

Design Flow (7) 5. Analog and mixed-signal circuit design: OpAmp, OTA, comparator circuits, analog mux, integrator circuits, S/H circuits, etc. Continuous-time or switched capacitor circuits Selecting the circuit topology, transistor sizing, and layout design 6. Digital circuit design: Customized digital circuits Interfacing circuits, digital filters, decimator circuits, encoders - like Huffman encoders for multimedia, etc. Complex digital sub-systems go through top-down design Simple circuits: logic design, mapping to basic circuits, transistor sizing, and layout design ©Alex Doboli 2006

Design Flow (8) 7. Software development: Application software and system software Data processing, control, and graphical user interfaces (GUIs) Real-time OS, middleware, and networking. 8. Circuit modeling: Characterizing the behavior of hardware Electronic circuits have significant differences from ideal behavior Nonidealities of analog and digital circuits propagation delay, power consumption, noise margins, gain, poles, zeros, bandwidth, harmonic distortion, circuit noise Different kind of nonidealities have to contemplated at different abstraction levels of a top-down design flow ©Alex Doboli 2006

Design Flow (9) 9. Software characterization: Prediction of the performance of software routines speed, memory, memory access patterns, power consumption, and so on Difficult due to the dynamic nature of software performance if statements, case statements, loops 10. Performance evaluation: Performance attributes of the system and its modules Quality of different design options without actually building, testing and measuring the designs Analytical expressions Simple to use, but require large development effort Prediction accuracy is not very high Simulation large simulation time ©Alex Doboli 2006

Embedded Systems Market 2003 2004 2009 % (2004-2009) Embedded software $1,4 bil $1,6 bil $3,4 bil 16 Embedded hardware $34,6 bil $40 bil $78,7 bil 14 Embedded boards $3,6 bil $5,9 bil 10 Total $39,4 bil $45,8 bil $88,1 bil Source: BCC Research Group, “Future of Embedded Systems Technology”, 2005 ©Alex Doboli 2006

What is an embedded system? (1) Fan controller: The controller adjusts the fan speed depending on the room temperature ©Alex Doboli 2006

What is an embedded system? (2) Functionality of the fan controller: The controller selects among four different predefined speed values (e.g., off, low, ramp, and high): If the room temperature stays below 25C then the fan stays off If the temperature is in the range 25C - 35C then the fan rotates at a low speed. For the temperature range 35C to 50C the speed of the fan linearly increases with the temperature following a ramp law Speedfan = room temperature / 10 The fan speed is set to high, if room temperature exceeds 50C LCD displays the temperature & the fan speed set by the controller Is that all? ©Alex Doboli 2006

What is an embedded system? (3) Embedded control algorithm Digital actuation Sensing Is that all? ©Alex Doboli 2006

Signal sensing/Data acquisition What signal (voltage, current)? Signal characteristics (range, frequency, noise, distortion) Signal loading characteristics (high impedance) Timing between pulses Interfacing (interrupts) Standards (I2C, RS232) Number of I/O Pins ©Alex Doboli 2006

Actuation Control signals Drive frequency Drive polarity Spin up time ©Alex Doboli 2006

Fan Controller Design Process (1) A. System specification Description of interfaces, functionality and performance requirements Specification notation/language B. Specification testing & debugging Specification debugging & validation (correctness & completeness) C. System implementation Analog & digital circuits Software (embedded control, drivers, ISR) D. Implementation testing and debugging ©Alex Doboli 2006

Fan Controller Specification (2) PSoC Express offers graphical interface for specification of certain mixed-signal systems Interconnect of modules Library of predefined modules Temperature sensor interface Control algorithm I/Os to pins ©Alex Doboli 2006

Controller Implementation (3) ©Alex Doboli 2006

Controller Implementation (4) ©Alex Doboli 2006

Implementation Debugging & Validation (1) Eliminate the faults in the implementation (e.g., system does not work) Analog, digital, software, integration etc. What input data activates a fault and propagates it to the output? Implementation Validation Is the implementation equivalent to the specification? Are all possible input values handled correctly? Is the functionality correctly realized? Are performance requirements met? How does the system operate in exceptional situations? ©Alex Doboli 2006

Implementation Debugging & Validation (2) Fix the number of bytes to be displayed on the LCD, their address, and amount Temperature & RPM Change Vref & monitor data on LCD LCD can display only limited amount of data ©Alex Doboli 2006

Implementation Debugging & Validation (3) HyperTerminal Connected through the serial port Steps for monitoring: Reset the system Set the duty cycle to 100% Define the I2C address and count value to be displayed HyperTerminal displays the registers for Fan, Tach, SPR, and Temp ©Alex Doboli 2006

Conclusions ©Alex Doboli 2006

Performance Improvement through Customization Alex Doboli, Ph.D. Department of Electrical and Computer Engineering State University of New York at Stony Brook Email: adoboli@ece.sunysb.edu ©Alex Doboli 2006

Overview of the Chapter Design methods for optimizing the system performance through architecture customization to the application characteristics Design methodology for execution time speedup of time critical applications Considered architecture: one processor and one co-processor Steps: specification, profiling, identification of performance-critical blocks, functional partitioning, hardware-software partitioning, hardware resource allocation, mapping to resources, scheduling PSoC programmable blocks supporting customization: Programmable digital blocks Blocks with dedicated functionality: PWM, MAC, Decimator ©Alex Doboli 2006

Application Specific Customization Design methods for optimizing the system performance through architecture customization to the application characteristics A block (Subroutine) is critical with respect to performance P, if P changes significantly with the modification of the block Customization to reduce the system execution time Related design steps: Profiling Selecting the blocks in HW Finding the nature of the used HW circuits Implementing the system ©Alex Doboli 2006

Implementing the System Layered implementation for reusability: Circuit layer Low-level firmware layer: ISR, drivers, physical addresses & data (bits, registers) High-level firmware level (API):used in applications, symbolic names, abstract data Application layer ©Alex Doboli 2006

Design tasks Architectures with single CPU and associated coprocessors: Critical parts are implemented as dedicated coprocessors Tasks: Hardware-software partitioning Hardware resource allocation Architectures with single CPU and shared coprocessors: Critical parts share hardware (lower cost, some performance loss) Binding (mapping) of blocks to hardware Scheduling ©Alex Doboli 2006

Design tasks Architectures with multiple CPUs and shared coprocessors: Multimedia, image processing, telecommunications Tasks: Hardware-software partitioning Allocating CPUs Allocating interconnect structure Hardware resource allocation Binding (mapping) of critical blocks to hardware Mapping software to CPUs Mapping data communications to interconnect Scheduling Etc. ©Alex Doboli 2006

Design Flow ©Alex Doboli 2006

Discussed Design Methodology Related design tasks: Specification and performance profiling Hardware-software partitioning Hardware resource allocation Binding (mapping) of critical blocks to hardware Scheduling ©Alex Doboli 2006

Processor-Coprocessor Architecture ©Alex Doboli 2006

Data Intensive Application Application characteristics: Data dominated: large number of computations Known number of loop iterations Iterations are uncorrelated or with few correlations (can be eliminated through transformations) ©Alex Doboli 2006

Array Organization in Memory Two dimensional arrays are stored at consecutive memory addresses A[m][n] is at index i = m x SZ + n Assumption: data length = memory word length (e.g., one byte for PSoC) ©Alex Doboli 2006

Profiling Related Steps: Produce assembly code More precise determination of execution time & memory requirements (code & data) Can be done statically Functional partitioning Hardware related code re-organization Code organized as blocks, where each block is a well-defined HW circuit Find the performance critical blocks Find system performance sensitivity with respect to the individual blocks ©Alex Doboli 2006

Block Structure ©Alex Doboli 2006

Refined Block Structure ©Alex Doboli 2006

Customized Hardware ©Alex Doboli 2006

Customized Hardware Hardware for Blocks 10-1 and 11-1: ©Alex Doboli 2006

Customized Hardware Data path for Blocks 10-1 and 11-1 ©Alex Doboli 2006

Customized Hardware Controller circuits for Blocks 10-1 and 11-1 ©Alex Doboli 2006

Controller ©Alex Doboli 2006

Customized Hardware Controller circuit for Blocks 10-1 and 11-1 ©Alex Doboli 2006

Counter Functionality ©Alex Doboli 2006

Data Flow Graph ©Alex Doboli 2006

Scheduling ©Alex Doboli 2006

Programmable Digital Blocks ©Alex Doboli 2006

Programmable Digital Block ©Alex Doboli 2006

Programmable Digital Block Programmable digital block inputs: DATA (primary input): RI (4 bits) – connections to GPIO, DB RO (4 bits) Broadcast: BCROW (4 rows) ACMP (comparator outputs) Input of the previous block High, Low AUX (auxiliary input): RI (4 bits) PO (primary output): GOO GOE ©Alex Doboli 2006

Programmable Digital Block Programmable digital block inputs: AO (auxiliary output): RO (4 bits) CLK (separate for each digital block): SYSCLKX2 CLK32 VC1, VC2, VC3 Broadcast RI RO Low, High CLK of previous digital block ©Alex Doboli 2006

Programmable Digital Blocks Related registers: Data: DR0, DR1, DR2 Function: CR0, FN Inputs: IN Outputs: OU Interrupts: INT Functions: timer, counter, deadband, CRC ©Alex Doboli 2006

Related Registers: registers DRx Related registers: DR0, DR1, DR2 Register DBB00 DBB01 DCB02 DCB03 DR0 0,20H 0,24H 0,28H 0,2CH DR1 0,21H 0,25H 0,29H 0,2DH DR2 0,22H 0,26H 0,2AH 0,2EH ©Alex Doboli 2006

Related Registers: registers DRx Related registers: DR0, DR1, DR2 Register DBB10 DBB11 DCB12 DCB13 DR0 0,30H 0,34H 0,38H 0,3CH DR1 0,31H 0,35H 0,39H 0,3DH DR2 0,32H 0,36H 0,3AH 0,3EH ©Alex Doboli 2006

Related Registers: registers DRx Related registers: DR0, DR1, DR2 Register DBB20 DBB21 DCB22 DCB23 DR0 0,40H 0,44H 0,48H 0,4CH DR1 0,41H 0,45H 0,49H 0,4DH DR2 0,42H 0,46H 0,4AH 0,4EH ©Alex Doboli 2006

Related Registers: registers DRx Related registers: DR0, DR1, DR2 Register DBB30 DBB31 DCB32 DCB33 DR0 0,50H 0,54H 0,58H 0,5CH DR1 0,51H 0,55H 0,59H 0,5DH DR2 0,52H 0,56H 0,5AH 0,5EH ©Alex Doboli 2006

Related Registers: registers CR0 & FN Related registers: CR0 and FN Register DBB00 DBB01 DCB02 DCB03 CR0 0,23H 0,27H 0,2BH 0,2FH FN 1,20H 1,24H 1,28H 1,2CH ©Alex Doboli 2006

Related Registers: registers CR0 & FN Related registers: CR0 and FN Register DBB10 DBB11 DCB12 DCB13 CR0 0,33H 0,37H 0,3BH 0,3FH FN 1,30H 1,34H 1,38H 1,3CH ©Alex Doboli 2006

Related Registers: registers CR0 & FN Related registers: CR0 and FN Register DBB20 DBB21 DCB22 DCB23 CR0 0,43H 0,47H 0,4BH 0.4FH FN 1,40H 1,44H 1,48H 1,4CH ©Alex Doboli 2006

Related Registers: registers CR0 & FN Related registers: CR0 and FN Register DBB30 DBB31 DCB32 DCB33 CR0 0,53H 0,57H 0,5BH 0,5FH FN 1,50H 1,54H 1,58H 1,5CH ©Alex Doboli 2006

Related Registers: registers IN & OU Related registers: IN and OU Register DBB00 DBB01 DCB02 DCB03 IN 1,21H 1,25H 1,29H 1,2DH OU 1,22H 1,26H` 1,2AH 1,2EH ©Alex Doboli 2006

Related Registers: registers IN & OU Related registers: IN and OU Register DBB10 DBB11 DCB12 DCB13 IN 1,31H 1,35H 1,39H 1,3DH OU 1,32H 1,36H 1,3AH 1,3EH ©Alex Doboli 2006

Related Registers: registers IN & OU Related registers: IN and OU Register DBB20 DBB21 DCB22 DCB23 IN 1,41H 1,45H 1,49H 1,4DH OU 1,42H 1,46H 1,4AH 1,4EH ©Alex Doboli 2006

Related Registers: registers IN & OU Related registers: IN and OU Register DBB30 DBB31 DCB32 DCB33 IN 1,51H 1,55H 1,59H 1,5DH OU 1,52H 1,56H 1,5AH 1,5EH ©Alex Doboli 2006

Interconnect ©Alex Doboli 2006

Interconnect ©Alex Doboli 2006

Row Digital Interconnect (RDI) ©Alex Doboli 2006

Programmable Clocks Clocks are programmed using register IN (bits 3-0) Synchronized with SYSCLK2 or SYSCLKx2 Programmed using register OU (bits 7-6) ©Alex Doboli 2006

Timer Block ©Alex Doboli 2006

Timer Functionality Timer block functionality: Terminal count: Generates a signal with programmable timing frequency Write function Main timer function Generate interrupt Compare functionality: Write compare value Read compare value Compare function Interrupts Capture functionality: Read value in register DR0 ©Alex Doboli 2006

Timer Block Data Flow ©Alex Doboli 2006

Main Timer Functionality ©Alex Doboli 2006

Timing Diagram Useful for generating interrupts after certain amount of time Hardware support for implementing timing constraints maximum time range, minimum time range ©Alex Doboli 2006

Terminal Count Firmware Routines ©Alex Doboli 2006

Compare Functionality ©Alex Doboli 2006

Compare Function Firmware Routines ©Alex Doboli 2006

Capture Related Functionality ©Alex Doboli 2006

Counter Functionality ©Alex Doboli 2006

Dead Band Circuit ©Alex Doboli 2006

Pulse Width Modulation (PWM) Function: produces signal with programmable period and pulse width enabled Inverted/noninverted counter Enable BC Interrupt (TC/compare) standalone Compare value Duty cycle = Pulse width / Period ©Alex Doboli 2006

PWM Firmware Functions Possible functions: PWM_Start PWM_Stop PWM_Write_PulseWidth PWM_WritePeriod PWM_bReadCounter PWM_bReadPulseWidth PWM_EnableInterrupts PWM_DisableInterrupts Programmable blocks: counter ©Alex Doboli 2006

PWM Firmware Functions ©Alex Doboli 2006

PWM Firmware Functions ©Alex Doboli 2006

PWM Firmware Function ©Alex Doboli 2006

PWM API ©Alex Doboli 2006

Software PWM Off time Pulse width ©Alex Doboli 2006

Software PWM Tuning capabilities: Fine (in steps of 12 cycles) Coarse (in steps of 30 cycles) Minimum Pulse width is 30 clock cycles Minimum period is 60 clock cycles Not a solution if faster signals are needed ©Alex Doboli 2006

Multiple Accumulate Circuit (MAC) Functionalities (selected using operands): Fast multiplication (uses regs MUL_X and MUL_Y) Multiplication followed by summing (MAC_X and MAC_Y) Fast multiplication Multiply-accumulate ©Alex Doboli 2006

Exercise: Scalar Product (C code) ©Alex Doboli 2006

Object Code from C Compiler ©Alex Doboli 2006

Object Code from C Compiler ©Alex Doboli 2006

Assembly Code without MAC ©Alex Doboli 2006

Assembly Code using MAC ©Alex Doboli 2006

Assembly code without MAC Experimental Results Execution time for different implementations (in clock cycles) Vector size C code without MAC C code with MAC Assembly code without MAC Assembly code with MAC 16 8958 6043 2861 390 64 45177 23659 11932 1580 256 - 52268 6188 in addition, 1494 clock cycles for initialization ©Alex Doboli 2006

differentiation at rate B/M H(z) = (1/M)2 [1 / (1-z-1)]2 (1 – z-M)2 Decimator Blocks Functionality: differentiation at rate B/M Integration at rate B H(z) = (1/M)2 [1 / (1-z-1)]2 (1 – z-M)2 Digital low pass filtering and down-conversion Used in down-sampling after DS modulators Incremental ADC ©Alex Doboli 2006

Resolution vs. M ©Alex Doboli 2006

Type 1 Decimator Circuit First integration Second integration input Functionality: single or double integration; differentiation is in software ©Alex Doboli 2006

Type 2 Decimator Circuit Realizes integration and differentiation Results in register DEC_DH (0, E4H) & DEC_DL (0, E5H) writing to registers DEC_DH and DEC_DL clears the accumulator Programming using registers DEC_CR0, DEC_CR1, and DEC_CR2 ©Alex Doboli 2006

Type 2 Decimator Register DEC_CR0 (0, E6H): Selects analog comparator column that is gated (bits IGEN) for incremental ADC Selects gating signals from digital block (bit ICLKS0) For incremental ADC Selects analog comparator column (bits DCOL) Selects clock for decimator registers (bit DCLKS0) Register DEC_CR1 (0, E7H): Used for incremental ADC or DS ADC (bit ECNT) Selects gating signals (bits ICLKS) Selects clock for decimator registers (bit DCLKS) Selects digital block latch (bit IDEC) ©Alex Doboli 2006

Type 2 Decimator Register DEC_CR2 (1, E7H): Selects mode: type 1, incremental ADC, type 2 (bits Mode) Data output shifting: no shift, one position shift, two positions shift, four positions shift (bits Data out shift) Semantics of input data (bits Data format) for addition Input ‘1’ is always interpreted ‘1’ Input ‘0’ is ‘-’1’ or ‘0’ Select the decimator rate M (bits Decimation rate) Off, 32, 50, 64, 125, 128, 250, 256 ©Alex Doboli 2006

Decimator Circuit ©Alex Doboli 2006

Programmable Data Communication Blocks Alex Doboli, Ph.D. Department of Electrical and Computer Engineering State University of New York at Stony Brook Email: adoboli@ece.sunysb.edu ©Alex Doboli 2006

Overview of the Chapter Design methods for optimizing the communications subsystems SPI and UART modules (Hardware & software) Communication subsystems are a main component of a system Influence system speed and power consumption API routines: channel configuration & management, data sent/receive Design methodology for optimized implementation Required primitives, available hardware, performance Selecting the modules, sharing, module implementation ©Alex Doboli 2006

Abstract Data Channels Communication blocks: Connections to peripherals Connections to other embedded systems Connections between the cores (of the same system) Standardized Set of high-level primitives for communication (abstract data channels) ©Alex Doboli 2006

High Level Primitives Possible primitives: Send (blocking, non-blocking) - IsOverrun NewTokenSent - IsEmpty Receive (blocking, non-blocking) - Enable/Disable Interrupts NewTokenReceived ConfigureCommunication ©Alex Doboli 2006

Example of Communicating Modules Characteristics: long idle times low utilization of HW (sharing, non-blocking primitives, interrupts) Data loss (different execution speeds) synchronization (low speed) ©Alex Doboli 2006

Channel Implementation Units Required communication primitives Performance Communication bandwidth Bandwidth = (number of information bits per frame / total number of bits per frame ) x 1 / bit time Baud rate (1 / bit time) Design constraints Global clock (synchronous, asynchronous) Number of physical links (# of pins, serial, parallel, full-duplex, half-duplex, simplex) Noise level (redundant information, parity bits, CRC, checksum) ©Alex Doboli 2006

Channel Implementation Units Design goal: find optimized designs such that Communication primitives are implemented Required HW is available Performance requirements are met (e.g., bandwidth) Other constraints are met (cost, 3 of I/O pins, etc) Standardized protocols Modules are from a library Design procedure: matching abstract channels to the communication modules from the library ©Alex Doboli 2006

Channel Implementation Units Channel Implementation Unit (CIU): CIUi = <Primitvesi, Hwresourcesi, Performacei, Constraintsi> Library: CHLibrary = {CIU1, CIU2, CIU3, …, CIUM} Examples: SPI, UART, 1-wire, 9-bit UART, coding/error correction, PCI etc. ©Alex Doboli 2006

Hardware-Software Implementation of CIUs Design method: Select the CIUs that can implement the abstract channels Find the abstract channels that share a CIU Develop HW-SW implementation for missing modules Performance attributes: Bandwidth, communication delay, average load, peak load, I/O pins, clock frequency, buffer memory, cost ©Alex Doboli 2006

Hardware-Software Implementation of CIUs CIU allocation: For each abstract channel, identify the library modules that can be used in implementation Look at primitives, performance, needed HW, constraints Abstract channel mapping: Find abstract channels that can share a CIU (reduces cost) Scheduling (arbitration) Buffer insertion Glue and control logic for sharing Developing (missing) CIUs: Missing primitives Performance requirements are not met by available modules ©Alex Doboli 2006

Hardware-Software Implementation of CIUs ©Alex Doboli 2006

Hardware-Software Implementation of CIUs CIU allocation: APrimitivesj  Primitivesi APerformancej  Performancei Hw resourcesi  available hardware Constraintsi  {k Constraintsk  Environment}  Abstract channel mapping: Initial abstract channel mapping Mapping improvement (sharing, alternative CIUs) Initial mapping: Find CIU of minimum hardware cost (conflicting constraints) Map more constrained channels first Best bandwidth – cost ratio first RCIj = max {Performace I / HW resources i} Constraints might be violated (# I/O pins, not minimum HW cost) ©Alex Doboli 2006

Hardware-Software Implementation of CIUs Mapping improvement: Merge two channels CIm and Cin Primitives can be delivered by a single module “Cumulated” performance can be met by the single module Scheduling policy: round-robin, highest priority channel first If performance not met, switch to a CIU with higher performance ©Alex Doboli 2006

Hardware-Software Implementation of CIUs Developing (missing) CIUs: ©Alex Doboli 2006

Serial Peripheral Interface (SPI) Characteristics: Full-duplex, synchronous, serial transmission SPI master (SPIM), SPI slave (SPIS) Communication: SPIM sends bits serially to SPIS Simultaneously, SPIS sends bits serially to SPIM SPIM generates clock signal (SCLK) for SPIS SPIM generates select signal (SS) for SPIS ©Alex Doboli 2006

PSoC SPI Blocks SPIM & SPIS: SW / hardware ©Alex Doboli 2006

PSoC SPIM SPIM data flow: ©Alex Doboli 2006

SPIS SPIS data flow: ©Alex Doboli 2006

PSoC SPI Operation Clocks: Internal clock INT_CLK (TINT_CLK = 2 x TCLK) INT_CLK used to produce SCLK (AO) SCLK starts if SPIM is enabled, and stops if SPIM is disabled Non-inverting (idle on ‘0’) / inverting clock (idle on ‘1’) Serial transmission and reception: Registers DR0 (shift), DR1 (TX), DR2 (RX) Initiate transmission: load byte to TX SPIM: Latch (receive) one bit on rising (falling) clock edge, shift (transmit) one bit on falling (rising) clock edge SPIS: latch on rising clock edge, shift on falling clock edge Mode 0 (rising & non-inverting), Mode 1 (rising & inverting), Mode 3 (falling & non-inverting), Mode 4 (falling & inverting) Set-up time: Tset-up = 0.5 TINT_CLK ©Alex Doboli 2006

SPI Implementation SPI Timing diagram: ©Alex Doboli 2006

SPI Operation ©Alex Doboli 2006

PSoC SPI Programming Register FN: Bits 2-0: “110” -> SPI (both SPIM and SPIS) Bit 3: “0” -> SPIM, “1” -> SPIS Bit 4: “0” -> interrupt on TX Reg Empty (new byte can be loaded to TX), “1” -> SPI Complete (new byte received) ©Alex Doboli 2006

PSoC SPI Programming Register CR0: Bit 0: Enable/Disable Bit 1: “0” -> non-inverting clock, “1” -> inverting clock Bit 2: ‘0’ -> latching on rising clock, ‘1’ -> latching on falling clock Bit 3: RX_Reg_Full (‘0’ -> RX empty, ‘1’ -> RX full) Bit 4: TX_Reg_Empty (‘0’ -> TX has 1 byte, ‘1’ -> TX empty) Bit 5: SPI Complete (‘1’ -> byte was shifted out, ‘0’ -> otherwise) Bit 6: RX Overrun (‘0’ -> no overrun, ‘1’ overrun) Bt 7: ‘0’ -> MSB first, ‘1’ -> LSB first ©Alex Doboli 2006

SPI Communication of Multiple Bytes (SW) Max 0.86 Mbits/sec ©Alex Doboli 2006

SPI Communication of Multiple Bytes (HW) Max 1.20 Mbits/sec (28% faster) ©Alex Doboli 2006

Software Routines (API) ©Alex Doboli 2006

Software Routines (API) ©Alex Doboli 2006

Software Routines (API) bitwise AND with masks: - SPI Complete – 0x20 - Overrun – 0x40 - TX Reg Empty - 0x10 - RX Reg full - 0x08 ©Alex Doboli 2006

Software Routines (API) Enable / disable interrupts: SPIM_EnableInt; SPIS_EnableInt SPIM_DisableInt; SPIS_DisableInt Enable / disable SS (ony SW controlled SS): SPIS_EnableSS SPIS_DisableSS ©Alex Doboli 2006

Example: Communicating Processes SPIM: ©Alex Doboli 2006

Example: Communicating Processes SPIS: ©Alex Doboli 2006

Universal Asynchronous Receiver Transmitter (UART) Characteristics: 8 bit, duplex, serial communication Communication: Two independent blocks: transmitter and receiver Implemented using 2 programmable PSoC blocks ©Alex Doboli 2006

PSoC UART Transmitter Receiver ©Alex Doboli 2006

PSoC UART Transmit Operation Clocks: Internal clock INT_CLK (TINT_CLK = 8 x TCLK) Serial transmission: Registers DR0 (shift), DR1 (TX), DR2 (RX), CR0 (control) Output = ‘1’, if no data in TX or block not enabled Transmit: data is loaded into TX, data loaded into the shift register, bits shifted out at each clock cycle Transmitted frame: bit start, 8 bits, parity bit, bit stop ©Alex Doboli 2006

UART Implementation UART Transmit Timing diagram: ©Alex Doboli 2006

UART Transmit Operation ©Alex Doboli 2006

PSoC UART Receive Operation Serial reception: Registers DR0 (shift), DR1 (TX), DR2 (RX), CR0 (control) Initiated by START bit (‘0’) One bit received at the rate equal to the set baud rate Finished after receiving STOP bit (‘1’): sets flag, data available in RX, back to the reception state Flags: RX Active (ongoing reception), RX Reg full (new byte received), Framing error, Parity error, Overrun ©Alex Doboli 2006

UART Implementation UART Receive Timing diagram: ©Alex Doboli 2006

UART Receive Operation ©Alex Doboli 2006

Software Routines (API) bitwise AND with masks: - RX Reg FULL – 0x08 - RX Parity Error – 0x80 - Overrun - 0x40 - Framing Error - 0x20 - Error – 0xE0 bitwise AND with masks: - TX Complete – 0x20 - TX Reg Empty – 0x10 ©Alex Doboli 2006

Example: Finding Status Flags ©Alex Doboli 2006

Example: Communicating Processes ©Alex Doboli 2006

Switched Capacitor Blocks Alex Doboli, Ph.D. Department of Electrical and Computer Engineering State University of New York at Stony Brook Email: adoboli@ece.sunysb.edu ©Alex Doboli 2006

Overview of the Chapter Introduction to SC circuits Programmable SC blocks in PSoC SC principle: controlled movement of charge Electrical nonidealities: circuit nonidealities, non-zero switch resistance, channel charge injection, clock feedthrough Basic SC blocks: gain amplifier, programmable gain amplifier, comparator, integrator, differentiator PSoC’s programmable SC blocks: Type C and Type D SC blocks Programming (registers) ©Alex Doboli 2006

Introduction to SC Techniques Integrated capacitors are easier to fabricate than resistors Average resistance approximated through charge movement I = V / R Q = C V Iaverage = Q fs = C V fs => Req = 1 / C fs ©Alex Doboli 2006

Introduction to SC Techniques Constraints: Switches Ф1 and Ф2 can never be closed at the same time Switch Ф1 must have time to open before switch Ф2 closes Switch Ф2 must have time to open before switch Ф1 closes Frequency fs must allow enough time for the circuits to fully charge and discharge ©Alex Doboli 2006

Non-idealities in SC Circuits Non-zero on-resistance of MOSFETs: d Vc(t) / d t = ID(t) / C Linear: d Vc(t) / d t = m Cox W [(VDD – Vc(t) - Vth)(Vin – Vc(t)) – (Vin – Vc(t))2 / 2] / 2 LC Vc(t) = (2 K exp (A Vin t) – A exp (A Vin t) + exp (kt + K[1])) Vin / (A exp (A Vin t) + exp (K t + K[1]) A = m Cox W / 2 L C K = A (VDD – Vth) Saturation:d Vc(t) / d t = m Cox W [(VDD – Vc(t) - Vth)(Vin – Vc(t)) – (Vin – Vc(t))2 / 2] / 2 LC Vc(t) = [(A t – C[1]) (VDD - Vth) - 1] / (A t – C[1]) Vc(0) = 0 => C[1] = - 1 / (VDD - Vth) Vc(t) = VDD – Vth – 1 / (a t – C[1]) ©Alex Doboli 2006

Non-idealities in SC Circuits Channel charge injection: Qchannel = W L Cox (VDD – Vin - Vth) D Vc = W L Cox (VDD – Vin - Vth) / C Trade-offs: Accuracy vs. speed (small W helps accuracy but decreases speed) ©Alex Doboli 2006

Non-idealities in SC Circuits Clock feedthrough: Capacitive coupling through Cgd D Vout = - Cgd,2 D VΦ2 Trade-offs: Accuracy vs. speed (small W lowers coupling but lowers speed too) ©Alex Doboli 2006

SC Fixed Gain Amplifier Characteristics: acquisition phase transfer phase ©Alex Doboli 2006

Acquisition & Transfer Phase Q = Vin CA Vout = - D Q / CF Gain = - CA / CF ©Alex Doboli 2006

Autozero Adjustment QAi = Voffset CA QAi + QFi = QAf + QFf QFi = Voffset CF QAf = (Vin – Voffset) CA QFf = (Voffset – Voutf) CF QAi + QFi = QAf + QFf Voutf = Voffset – [(CA + CF) Voffset – CA(Voffset - Vin)] / CF Voutf = - CA / CF Vin ©Alex Doboli 2006

SC Selectable Gain Polarity Amplifier ©Alex Doboli 2006

SC Comparator ©Alex Doboli 2006

SC Integrator ©Alex Doboli 2006

SC Integrator During acquisition: Q = Vin CA During transfer: Qtot = Q’ + Vin CA Vout (t) = Vout (t – Ts) + CA / CF Vin [Vout (t) - Vout (t – Ts)] / Ts = fs CA / CF Vin d Vout (t) / dt = CA / CF fs Vin Integrator gain: CA / CF fs ©Alex Doboli 2006

SC Differentiator ©Alex Doboli 2006

Improved Reference Selection ©Alex Doboli 2006

Improved Reference Selection Ground reference: Vout = Vin CA / CF Vref+ reference: Vout = (Vin – Vref+) CA / CF Vref- reference: Vout = (Vin – Vref-) CA / CF Integrator gain: CA / CF fs ©Alex Doboli 2006

Two Bit ADC ©Alex Doboli 2006

Two Bit ADC Vin > Vref+ Vin < Vref+ and Vin > 0 Vin < 0 and Vin > Vref- Vin < Vref- ©Alex Doboli 2006

Analog to Digital Conversion ©Alex Doboli 2006

Analog to Digital Conversion Reference is Vref+ if comparator output is 1 Reference is Vref- if comparator output is 0 Vouti = 0 Switch cycle is performed n times Comparator output is 1 a number of a times Vout = CA / CF [n Vin – a Vref+ - (n – a) Vref-] For Vref+ = - Vref- = Vref: Vin = Vref (2 a - n) / n + Vout CF /[ n CA] Vin = Vref (2 a - n) / n Resolution: Vref 2 / n ©Alex Doboli 2006

Switched Capacitor PSoC Blocks Each column: analog bus, comparator bus, clocks Φ1 and Φ2 ©Alex Doboli 2006

PSoC Type C Block ©Alex Doboli 2006

PSoC Type C Block Control registers: ASCxxCR0, ASCxxCR1, ADCxxCR2, ASCxxCR3 Functionality (gain, integrator, comparator) Input & output configuration Power mode Sampling procedure (positive / negative gain) OpAmp: 4 power modes (off, low, medium, high) Programmed through bits PWR (bits 1-0 of ASCxxCR3) Functionality programmed through bits FSW1 and FSW0 Bit FSW1: FCap connected or not (gain/integrator or comparator) Bit 5 of ASCxxCR3 Bit FSW0: FCap discharged or not (gain or integrator) Bit 4 of ASCxxCR3 ©Alex Doboli 2006

PSoC Type C Block 5. Programmable matrix arrays: ACap, BCap, CCap, FCap ACap value programmed through bits 4-0 of ASCxxCR0 Value: 0 – 31 units (1 unit ~ 50fF) Autozero bit: Autozeroing during Φ1 Bit 5 of ASCxxCR2 Asign bit: positive or negative gain Bit 5 of ASCxxCR0 Positive gain: input sampled on clock Φ1 Negative gain: input sampled on clock Φ2 Reference selection 6. BCap: BCap capacitor value: 0 – 31 units Bits 4 – 0 in ASCxxCR1 7. CCap: CCap capacitor value: 0 – 31 units Bits 4-0 in ASCxxCR2 ©Alex Doboli 2006

PSoC Type C Block 8. FCap: Value programmed through bit 7 of ASCxxCR0 Value: 16 or 32 units 9. Programmable inputs: Inputs to ACap, BCap, CCap are programmable Bits 7-5 of ASCxxCR1 Reference to ACap is also programmable Bits 7-6 of ASCxxCR3 AGND, Vref+, Vref-, comparator output (RefHi if comparator output is high, and RefLo if comparator output is low) ©Alex Doboli 2006

Programmable ACap Inputs ACMux ASC10 ASC21 ASB12 ASC23 000 ACB00 ASD11 ACB02 ASD13 001 ASD20 ASD22 010 RefHi 011 Vtemp ABUS3 100 ACB01 ACB03 ASC12 101 110 ABUS11 111 P2[1] P2[2] ACMux: bits 7-5 of ASCxxCR1 ©Alex Doboli 2006

Programmable BCap Inputs BCMux ASC10 ASC21 ASB12 ASC23 00 ACB00 ASD11 ACB02 ASD13 01 ASD20 ASD22 10 P2[3] P2[0] 11 TrefGND ABUS3 BCMux: bits 3-2 of ASCxxCR3 ©Alex Doboli 2006

Programmable CCap Inputs ACMux ASC10 ASC21 ASB12 ASC23 000 ACB00 ASD11 ACB02 ASD13 001 010 011 100 ASD20 ASD22 101 110 111 ACMux: bits 7-5 of ASCxxCR1 ©Alex Doboli 2006

PSoC Type C Block 10. Programmable outputs: Bit AnalogBus: Output to analog buffer Bit 7 of ASCxxCR2 Bit CompBus: Connects comparator output to digital block inputs Bit 6 of ASCxxCR2 11. Clocking scheme: Bit ClockPhase: Bit 6 of ASCxxCR0 External Φ1 or Φ2 is internal Φ1 ©Alex Doboli 2006

Type D Switched Capacitor Blocks ©Alex Doboli 2006

Type D Switched Capacitor Blocks Differences: CCap connected to the output, which connects to the suming node of the next SC C block (biquad filters) Switch BSW: BCap is either SC or fixed capacitor BCap connected to the summing node AnalogBus switch connects OpAmp output to analog buffer CompBus switchconnects comparator to the digital blocks BCap programmable capacitor sampled on Φ2 ©Alex Doboli 2006

Example: Differential amplifier with common mode input Vdifferential = PosInput – NegInput Vcommon = (PosInput + NegInput) / 2 ©Alex Doboli 2006

Example: Differential amplifier with common mode input ©Alex Doboli 2006

Analog to Digital Conversion ©Alex Doboli 2006

Isolated Analog Driver ©Alex Doboli 2006

DS Analog to Digital Converters Alex Doboli, Ph.D. Department of Electrical and Computer Engineering State University of New York at Stony Brook Email: adoboli@ece.sunysb.edu ©Alex Doboli 2006

DS ADC The chapter introduces the following aspects: Basic concepts of DS ADC & 1sr and 2nd order ADCs ADC are main subsystems in any embedded system DS ADC offer high resolution through two mechanisms: Oversampling: reduces in-band quantization noise Noiseshaping: eliminates in-band quantization noise PSoC implementation of DS ADC: modulator, decimator, API ©Alex Doboli 2006

Nyquist ADCs Embedded system front end: ©Alex Doboli 2006

Sampling Collect sufficient data for correctly representing a continuous-time signal ©Alex Doboli 2006

Nyquist Sampling Theorem A bandlimited signal can be exactly reconstructed if the sampling Frequency is greater than twice the signal bandwidth Nyquist frequency is twice the signal bandwidth ©Alex Doboli 2006

Xs(f) = X(f) + X(f+/-fs) + X(f+/-2fs) + X(f+/-3fs) + X(f+/-4fs) + … Sampling Xs(f) = X(f) + X(f+/-fs) + X(f+/-2fs) + X(f+/-3fs) + X(f+/-4fs) + … aliasing ©Alex Doboli 2006

Quantization Quantization is the process of converting the sampled continuous- Valued signals into discrete-valued data ©Alex Doboli 2006

Quantization Discretization range: D = 2 / (2B - 1) Quantization error: er ε (-D/2, D/2) White noise xd = xs + er ©Alex Doboli 2006

Quantization Error Quantization error is white noise & is uncorrelated to the input Bennett’s conditions: Input does not overload quantizer B is large D is small Joint probability density function of the input at various sampling moments is smooth ©Alex Doboli 2006

Quantization Error Power spectral density Quantization noise power s2e = D2 / 12 ©Alex Doboli 2006

DS Analog to Digital Converter ©Alex Doboli 2006

Oversampling Oversampling frequency Oversampling Ratio (OSR) Advantages of high OSR: simplifies elimination of the images reduced in-band noise power Pin-band = s2e / OSR ©Alex Doboli 2006

Noiseshaping Y(z) = H(z) / (1 + H(z)) X(z) + 1 / (1 + H(z)) E(z) STF NTF ©Alex Doboli 2006

DS ADC Performance Signal-to-noise ratio (SNR): SNR (dB) = 10 log (signal power) / (in band quantization noise power) For sinusoidal input: SNR (dB) = 6.02 B + 1.76 (dB) SNR (dB) = 6.02 B + 10 log OSR Dynamic range (DR): Ratio between the output power for a sinusoidal input with full-range amplitude and the output power of the smallest input signal that it can distinguish and quantize DR (dB) = 10 log (D2 / 8) / (in band quantization noise power) B (bits) = (DR (dB) – 1.76) / 6.02 ©Alex Doboli 2006

First-order DS Modulator yd(t) = z-1 x(t) + (1 – z-1) e(t) STF = z-1 NTF = 1 – z-1 ©Alex Doboli 2006

First-order DS Modulator: STF & NTF High pass ©Alex Doboli 2006

Power Spectrum Density Frequency of the input signal noise shaping ©Alex Doboli 2006

DS Modulator Performance In-band quantization noise power: Pin-band = p2 / (9 OSR3) Signal to noise ratio for sinusoidal input: SNR = 10 log (9 A2 OSR3) / (2 p2) ©Alex Doboli 2006

Dynamic Range 34 dB (5 bits) ©Alex Doboli 2006

Dynamic Range vs. OSR DR=34db (OSR=32) DR=38dB (OSR=64) (8 bits) ©Alex Doboli 2006

PSoC Implementation Vin  (-Vref, Vref) Vref  {VDD/2, 1.6 Vbandgap, Vexternal} OSR = 64 Vin = (n – 128) / 128 Vref ©Alex Doboli 2006

PSoC Implementation DS modulator Uses programmable SC blocks Decimator Low pass filtering (eliminates high frequency images) Downconversion by factor OSR Sinc2 filter Implementation: hardware (integration) – software (differentiation) Downconversion: timer produces an interrupt after OSR clock cycles & ISR implements differentiations API routines Clocks ©Alex Doboli 2006

Modulator Implementation Single clock for entire design (4 x OSR) ©Alex Doboli 2006

Measured PSD (OSR = 32) ©Alex Doboli 2006

Measured PSD (OSR = 64) ©Alex Doboli 2006

Sinc2 Decimator Filter (OSR=64) H(z) = [1 / OSR x (1 – z-OSR) / (1 – z-1) ]2 fb/2 + m fs/2 ©Alex Doboli 2006

Sinc2 Decimator Filter Integration: in hardware using Type 1 decimator block Differentiation: in software at downconversion rate (4 x OSR) Interrupts at 4 x OSR / fs ©Alex Doboli 2006

Timer ISR ©Alex Doboli 2006

API Routines ©Alex Doboli 2006

API Routines ©Alex Doboli 2006

Example ©Alex Doboli 2006

Modeling of jitter noise ©Alex Doboli 2006

Switch Thermal Noise ©Alex Doboli 2006

Switch Thermal Noise ©Alex Doboli 2006

Switch Thermal Noise ©Alex Doboli 2006

OpAmp Noise ©Alex Doboli 2006

Modeling of Slew Rate & Saturation ©Alex Doboli 2006

Second Order DS Modulator ©Alex Doboli 2006

Second-order DS Modulator ©Alex Doboli 2006

PSoC Implementation ©Alex Doboli 2006