UK Activities on pixels. (Previous report at Frascati, Dec 2009)

Slides:



Advertisements
Similar presentations
Monolithic Active Pixel Sensor for aTera-Pixel ECAL at the ILC J.P. Crooks Y. Mikami, O. Miller, V. Rajovic, N.K. Watson, J.A. Wilson University of Birmingham.
Advertisements

J.A. Ballin, P.D. Dauncey, A.-M. Magnan, M. Noy
H1 SILICON DETECTORS PRESENT STATUS By Wolfgang Lange, DESY Zeuthen.
ATLAS SCT Endcap Detector Modules Lutz Feld University of Freiburg for the ATLAS SCT Collaboration Vertex m.
March, 11, 2006 LCWS06, Bangalore, India Very Forward Calorimeters readout and machine interface Wojciech Wierba Institute of Nuclear Physics Polish Academy.
Workshop on Silicon Detector Systems, April at GSI Darmstadt 1 STAR silicon tracking detectors SVT and SSD.
LCWS 31/5/2007Erik Johnson STFC,RAL1 ILC Vertex Detector Mechanical Studies Erik Johnson On behalf of the LCFI collaboration STFC, Rutherford Appleton.
1 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory 1 ECFA 2006, Valencia 1 MAPS-based ECAL Option for ILC ECFA 2006, Valencia, Spain Konstantin.
The LHCb Inner Tracker LHCb: is a single-arm forward spectrometer dedicated to B-physics acceptance: (250)mrad: The Outer Tracker: covers the large.
Performance of the DZero Layer 0 Detector Marvin Johnson For the DZero Silicon Group.
SuperB Detector Summary SuperB Miniworkshop, Oxford 18/19 th May 2011
Rutherford Appleton Laboratory Particle Physics Department A Novel CMOS Monolithic Active Pixel Sensor with Analog Signal Processing and 100% Fill factor.
HFT & PXL geometry F.Videbæk Brookhaven National Laboratory 13/9/12.
STS Simulations Anna Kotynia 15 th CBM Collaboration Meeting April , 2010, GSI 1.
1 Conceptual design adopts state-of-the-art silicon sensor techniques (compare ATLAS/CMS/ALICE inner tracker layers, BaBar tracking of B mesons). Design.
The ALICE Silicon Pixel Detector Gianfranco Segato Dipartimento di Fisica Università di Padova and INFN for the ALICE Collaboration A barrel of two layers.
LCFI Collaboration Status Report LCUK Meeting Oxford, 29/1/2004 Joel Goldstein for the LCFI Collaboration Bristol, Lancaster, Liverpool, Oxford, QMUL,
Development of an ASIC for reading out CCDS at the vertex detector of the International Linear Collider Presenter: Peter Murray ASIC Design Group Science.
ATLAS PIXEL SYSTEM OVERVIEW M. Gilchriese Lawrence Berkeley National Laboratory March 11, 1999.
Thin Silicon R&D for LC applications D. Bortoletto Purdue University Status report Hybrid Pixel Detectors for LC.
Adrian Bevan Queen Mary, University of London SVT Mechanical Support and Strip Sensors.
Tevatron II: the world’s highest energy collider What’s new?  Data will be collected from 5 to 15 fb -1 at  s=1.96 TeV  Instantaneous luminosity will.
UK Activities on pixels. Adrian Bevan 1, Jamie Crooks 2, Andrew Lintern 2, Andy Nichols 2, Marcel Stanitzki 2, Renato Turchetta 2, Fergus Wilson 2. 1 Queen.
BTeV Hybrid Pixels David Christian Fermilab July 10, 2006.
STS simulations: Layout, digitizers, performance Radoslaw Karabowicz GSI.
M. Deveaux, CBM-Collaboration-Meeting, 25 – 28. Feb 2008, GSI-Darmstadt Considerations on the material budget of the CBM Micro Vertex Detector. Outline:
Rutherford Appleton Laboratory Particle Physics Department G. Villani CALICE MAPS Siena October th Topical Seminar on Innovative Particle and.
TC Straw man for ATLAS ID for SLHC This layout is a result of the discussions in the GENOA ID upgrade workshop. Aim is to evolve this to include list of.
WG3 – STRIP R&D ITS - COMSATS P. Riedler, G. Contin, A. Rivetti – WG3 conveners.
ILD Vertex Detector Y. Sugimoto 2012/5/24 ILD
Leo Greiner IPHC1 STAR Vertex Detector Environment with Implications for Design and Testing.
Walter Sondheim 6/9/20081 DOE – Review of VTX upgrade detector for PHENIX Mechanics: Walter Sondheim - LANL.
Ideas for Super LHC tracking upgrades 3/11/04 Marc Weber We have been thinking and meeting to discuss SLHC tracking R&D for a while… Agenda  Introduction:
Rene BellwiedSTAR Tracking Upgrade Meeting, Boston, 07/10/06 1 ALICE Silicon Pixel Detector (SPD) Rene Bellwied, Wayne State University Layout, Mechanics.
1 FANGS for BEAST J. Dingfelder, A. Eyring, Laura Mari, C. Marinas, D. Pohl University of Bonn
B => J/     Gerd J. Kunde PHENIX Silicon Endcap  Mini-strips (50um*2mm – 50um*11mm)  Will not use ALICE chip  Instead custom design based on.
I.Rashevskaya- SVT Meeting - Frascati SuperB SVT Strip Pairing: impact on the capacitance value Irina Rashevskaya, Luciano Bosisio, Livio.
L. Bosisio - 2nd SuperB Collaboration Meeting - Frascati SuperB SVT Update on sensor and fanout design in Trieste Irina Rashevskaya, Lorenzo.
The SuperB Silicon Vertex Tracker Abstract : The SuperB project aims to build an asymmetric e+ - e- collider capable of reaching.
Straw man layout for ATLAS ID for SLHC
Update on & SVT readout chip requirements
Si Sensors for Additional Tracker
SVT – SuperB Workshop – Annecy March 2010
Roberto Calabrese Ferrara University and INFN
for the SPiDeR collaboration (slides from M. Stanitski, Pixel2010)
Detector building Notes of our discussion
What does a τ-C experiment need from an SVT?
 Silicon Vertex Detector Upgrade for the Belle II Experiment
SVT subchapters & editors
Some input to the discussion for the design requirements of the GridPixel Tracker and L1thack trigger. Here are some thoughts about possible detector layout.
BaBar Silicon Tracker Perspective
Evidence for Strongly Interacting Opaque Plasma
SVT – SuperB Workshop – SLAC 6-9 Oct 2009
IBL Overview Darren Leung ~ 8/15/2013 ~ UW B305.
INFN Pavia and University of Bergamo
Hybrid Pixel R&D and Interconnect Technologies
SVT Mechanics Baseline SuperB SVT configuration
Silicon Pixel Detector for the PHENIX experiment at the BNL RHIC
HV-MAPS Designs and Results I
Adapting the via last Design
Update on SVT activities
The SuperB Silicon Vertex Tracker
SuperB SVT Definition of sensor design and z-side connection scheme
Work packages status in Torino and perspectives
Tracker Outer Barrel Silicon
Silicon tracker and sensor R&D for sPHENIX
SiD Tracker Concepts M. Breidenbach
SVT detector electronics
SVT – SuperB Workshop – Frascati Sept. 2010
Perugia SuperB Workshop June 16-19, 2009
Presentation transcript:

UK Activities on pixels. (Previous report at Frascati, Dec 2009) Adrian Bevan1, Jamie Crooks2, Andrew Lintern2, Andy Nichols2, Marcel Stanitzki2, Renato Turchetta2, Fergus Wilson2. 1Queen Mary, University of London 2STFC, Rutherford Appleton Laboratory

Overview Brief Reminder of the concept: Work since Frascati: Discussions with Pisa (March) Material Budget Geometries: Long Barrel Lampshade To Do... (a long list): Chip Support Physics studies Annecy March 09

TPAC-style sensor for SuperB Deep p-well pixel design (derived from TPAC). On pixel preamp, shaper, peak hold. Token seek readout logic. 5bit Ramp ADC per column of pixels to provide some dE/dx information (need to evaluate the impact from this). Preamp Shaper Rst Vth+ Vth- PkHold The PeakHold keeps data until pixel can be readout/reset. ~12μW static power per pixel. Annecy March 09

One digital read channel Digital bus J. Crooks Hit Pixel One digital read channel Digital bus Records row address of each token location Four parallel read channels Token seek logic Analog read line 1 2 3 4 FIFO ADC FIFO ADC Pipelined ADC 4 stages Row Data FIFO 4 stages FIFO ADC FIFO ADC Row Addr Hit Data

TPAC sensor for SuperB J. Crooks Data rates from Layer 0 are very high Consider an on-chip FIFO with external veto/trigger to reduce data volume Data rates from outer layers are much lower Consider a column multiplexer circuit that allows ADCs to be shared while others are powered down in outer layers Could use the same ASIC design with less connections (bonds) for outer layers? Annecy March 09

Sensor module for SuperB Alter layout of the chip: (4×2.5cm2 chip stitched together) 1 module = a 10cm × 2.5 cm × 50μm sensor. Radiation hardness should be acceptible~1013 n/cm2. 10 W power per module: < 5KW per 6 layer SVT. Requires active cooling. Ramifications for: Material Budget. Utility hook-up (cooling/power/readout). 10cm 50μm × 50μm pixel size 2.5cm Annecy March 09

Stave Drawings Electronics Sensors Cooling Concept: use staves as a basic unit for assembly of the detector. Design a rigid stave to be supported from the ends, with minimal saggital sag (250um). Electronics Sensors Cooling Annecy March 09

Material Budget: Some initial studies Made first go at Stave structure Sandwich Silicon 50 microns Carbon Fiber Silicon Carbide Foam Aluminum Cooling pipes Current Material budget 1.1 % per stave Dominated by carbon fiber Very conservative design Will be reduced after more FEA studies Expect bus material is about 250μm of Al/Kapton bus (as in FastSim for other solns.). Cu/Kapton Bus Si CF SiC Al + Water Need to determine realistic bus material budget Annecy March 09

Mechanical Layout The Lamp-Shade geometry can be adapted from this design – need to try barrel vs LS optimization studies to quantify any gains. Annecy March 09

Costs Expect a yield of ~60% This is based on previous experience with this foundry. Expect sensor cost of $0.5M / 330K€. Annecy March 09

Discussions with Pisa Marcel Stanitzki, Fergus Wilson, AB recently visited Pisa. Extremely useful meeting – many ideas exchanged. Concepts for lighter support structure. Geometry of the detector, and how to realise this. Visited the Pisa facilities to see the status of their R&D. Detailed list of things to investigate between now and the end of the TDR period (see later). Outlined a path for tighter collaboration between UK and Italian efforts. Annecy March 09

To Do List Work on the chip: How can we make LS end modules? While it is easy to make trapezoidal sensors with strips; this is harder for INMAPS. Can make a variant on Rectangular geometries. Started to think about geometry issues for the tapered ends of the LS setup. Bus cable is a solvable issue The CMOS structure – especially with stitching is a little more complicated... ? Easy to fabricate Not so clear cut Easy BaBar Outer Layer (Pisa) Annecy March 09

To Do List Work on the Chip: Radiation hardness. Power consumption vs. hit rate. Signal resolution as a fn of incident angle. Usefulness of dE/dx measurement from 50um of silicon (Re: ADC). Power distribution/signal bus over 30cm (utilities issue) & do we need coupling capacitors over this length. Cooling over 30cm (utilities issue) BaBar Outer Layer (Pisa) Annecy March 09

To Do List Work on the mechanics: L0 off bellows, L1-N off cryostat How much material in the bus. What is the material budget for inner/outer layers (between 0.2 and 1.14%). Half shell space-frame geometry with overlapping sensors to minimize material budget? What would the material budget of this be vs. stave design? Retain pinwheel for the silicon sensors (50um thick). Superstructure would support sensors at ends (struts in the middle as/if needed). Cooling infrastructure would support the sensor along z (into page). Annecy March 09

To Do List Work on physics studies: Study low level information on particle tracking: d0, ... Low momentum tracking performance Affect on θC resolution in DIRC from material. Study a number of modes to see how each design choice affects the potential output: π+π−, π0π0, D*X (soft pions), D-mixing (at 4S and threshold), τν &/ Kνν [aim to define Barrel and LS geometries in Fast Sim to check signal performance] Study the material budget as a function of θ, etc. ... using particle gun modes of FastSim and Bruno. Physics benefit of r=1.3 vs. r=1cm. Annecy March 09

Summary Already had some good ideas to go away and think about as possible variant concepts on the support. A natural to tie in with work from Filippo Bosi. Now need to knuckle down and do some more work... Aim to define a long barrel and lampshade design for signal studies in the simulation programmes as soon as we define the amount of bus material. As we understand the mechanics of the space-frame geometry, will put a geometry together on that as well. A lot of work to do! Annecy March 09