3D IC Technology

Contents Limits of 2D 3D-IC Benefits 3D-IC Technology May 18

Limits of 2D May 18

Limits of 2D 1D gate to 3D gate MOS devices start “3D” in 22 nm technology Current drive (mA/µm) 2.0 1.0 0.0 130 nm 1.5 0.5 45 nm 65 nm 22 nm 32 nm 17 nm Technology node Strain Gate material 90 nm Strain to increase mobility High K Metal Gate to increase field effect Tri-Gate for increasing drive current and reducing leakage May 18

Limits of 2D Giga-device to its limits 2D 2.5D 3D 2004 130nm 100M Core+ DSP 1 Mb Mem 2006 90nm 250M Core DSPs 10 Mb Mem 2008 45nm 500M Dual core Dual DSP RF Graphic Process. 100 Mb Mem Sensors 2010 32nm 2G Quad Core Quad DSP 3D Image Proc Crypto processor Reconf FPGA, Multi RF 1 Gb Memories Multi-sensors 22nm 2012 7G 5nm 150 G 2020 ? Technology Complexity Packaging Embedded blocks

Adapted from ITRS roadmap for semiconductors, 2011 Limits of 2D Needs for improved protection, but noise margins reduced 500 mV margin 100 mV margin Supply (V) 5.0 3.3 I/O supply 2.5 Core supply 1.8 1.2 1.0 0.5µ 0.35µ 0.18µ 130n 90n 65n 45n 32n 22n 17n Technology Adapted from ITRS roadmap for semiconductors, 2011 May 18

Limits of 2D Needs for improved reliability but reduced operating windows IESD IEMC Destruction IC vulnerability Thermal stress Safe ESD protection window IC non-linear susceptibility IC operation area IC Reliability constraints VESD VEMC IC linear susceptibility Adapted from “Lowering Component Level HBM/MM ESD Specifications and Requirements”, Industry Council on ESD Target Levels, White Paper 2007 May 18

3D-IC BENEFITS May 18

3D-IC Benefits “Evolutionary and revolutionary interconnect technologies are needed to enable migration to 3D” ITRS 2009 - The next Step in Assembly and Packaging: System Level Integration in the package, white paper May 18

3D-IC Benefits Georgia-Tech vision of SoC From Georgia Tech 3D system packaging research http://www.prc.gatech.edu. May 18

From 3DIC & TSV Report Cost, Technologies & Markets, 2007, Yole Dev. 3D-IC Benefits “The integration of 3D technologies will enable performances, form factor and cost requirements of the next generation of electronic” devices From 3DIC & TSV Report Cost, Technologies & Markets, 2007, Yole Dev. May 18

From 3DIC & TSV Report Cost, Technologies & Markets, 2007, Yole Dev. 3D-IC Benefits One new piece in the puzzle From 3DIC & TSV Report Cost, Technologies & Markets, 2007, Yole Dev. May 18

From ITRS 2011 Executive Summary, and Yole Dev. 3D-IC Benefits 3D Packaging contributes to “More than Moore” at a reasonable price 2008 : “Why 3D?” 2010 “”How 3D? 2012 : “When 3D?” … 20xx : “Why 2D?” From ITRS 2011 Executive Summary, and Yole Dev. May 18

3D-IC Benefits 3D technology enables the integration of ICs fabricated in different technologies CMOS, CCD, SOI, Sensor 4µm vias Bosch process B. Aull, et. al., “Laser Radar Imager Based on 3D Integration of Geiger-Mode Avalanche Photodiodes” IEEE SSCC 2006. C. Bower, et. al., “High Density Vertical Interconnects for 3D Integration of Silicon ICs,” 56th ECTC, San Diego, 2006. 0.18μm SOI 0.35 μm SOI Sensor May 18

3D-IC Benefits Improve electronic efficiency 3D minimizes interconnect parasitic effects 3D simplifies multiple supply voltage distribution 3D reduces package pin count More uniform, high density power delivery J. Lu, “Monolithic 3D Power Delivery Using Dc-Dc Converter”, 3D Architecture Conference, October, 2006, Burlingame, CA. May 18

3D-IC Benefits A significant increase in bandwidth 2D 3D Buffer 3-stage 1-stage Pad Load 3-5 pF 1 pF Interconnect capa 5-20 pF 0.1-1 pF Interconnect inductance 5-30 nH 0.1-1 nH Current drive 10-100 mA 1-10 mA May 18

Voltage translation and level shifers 3D-IC Benefits A significant reduction in I/O complexity Solder ball ESD protection Voltage translation and level shifers May 18

3D-IC Benefits A better power efficiency Smaller wire-length distribution Shorter wires decrease the average load capacitance and resistance and decrease the number of repeaters needed for long wires. The reduced average interconnect length in 3D IC, vs 2D IC, improves the wire efficiency by 15-25 % Active power may be reduced by 25-50% "Implementing a 2-Gbs 1024-bit ½-rate Low-Density Parity-Check Code Decoder in 3D-Ics « , Lili Zhou, ICCD 2007 T. Topol « Three-dimensional integrated circuits », Ibm Journal Research, 2006 May 18

3D-IC Benefits 2.5D ICs The yield of a single 7-Billion CMOS die is too low 4 dies (1.7 B-device each) connected by transposer The 4-die Virtex-7 reaches 7 Billion devices May 18

From ITRS 2009 Assembly and Packaging. 3D-IC Benefits Tera-Hertz computing in 2015 From ITRS 2009 Assembly and Packaging. May 18

3D-IC Benefits The HE physisict dream… Atlas photon detector at CERN The HE physisict dream… High Energy Physics requires sophisticated detectors integrating sensors readout electronics. Review of 3D Related Technologies for HEP, R. Yarema, 2007 May 18

3D-IC TECHNOLOGY May 18

3D-IC Technology Higher complexity at lower cost Stacking of memories 12 chips, 840 µm thickness 8 chips, 560 µm thickness May 18

From 3DIC & TSV Report Cost, Technologies & Markets, 2007, Yole Dev. 3D-IC Technology Interposers Based on silicon or glass Replace traditional PCB laminate or ceramic technologies Alternative to very large 2D ICs at prohibitive costs Very high density and bandwidth “Bridge” platform between 2D and 3D Pitch (µm) From Georgia Tech 3D system packaging research http://www.prc.gatech.edu. From 3DIC & TSV Report Cost, Technologies & Markets, 2007, Yole Dev. May 18

3D-IC Technology Direct bond interconnect (DBI) using magic metal R around 50 mΩ Review of 3D Related Technologies for HEP R. Yarema, 2007 Ziptronix, 3D Conference, Oct, 2007 May 18

3D-IC Technology Wire-Bond vs. Through-Silicon-Via (TSV) LOH, « 3D Stacked Microprocessor: Are We There Yet? », IEEE Micro, 2010 A. Chambers, “Through-Wafer Via Etching”, Advanced Packaging, April 2005 May 18

3D-IC Technology Source: Yole Dev. May 18

3D-IC Technology Terrazon with « super contact » May 18

Process offered by CMC, CMP and MOSIS 3D-IC Technology Process offered by CMC, CMP and MOSIS Terrazon with 2 flip chips May 18

3D-IC Technology IC design with Direct Bond Interconnect (DBI) From CMP annual users meeting, “3D-IC Integration”, January 20th 2011, PARIS May 18

Development of 3D Integrated Circuits for HEP, R. Yarema 3D-IC Technology Via formation for die to wafer process Development of 3D Integrated Circuits for HEP, R. Yarema May 18

MIT Lincoln Labs 3D case study 3D-IC Technology MIT Lincoln Labs 3D case study R. Yarema, “Development of 3D Integrated Circuits for HEP”, 12th LHC Electronics Workshop, Valencia, Spain, September 25-29, 2006 May 18

3D-IC Technology Development of 3D Integrated Circuits for HEP, R. Yarema, 2006 3D IC Pixel Electronics, the Next Challenge, R. Yarema, 2008 May 18