IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-based FPGAs

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Presentation transcript:

IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-based FPGAs Zhe Feng1, Naifeng Jing2, GengSheng Chen3, Yu Hu4, and Lei He1 1. Electrical Engineering Department, University of California, Los Angeles 2. School of Microelectronics, Shanghai Jiao Tong University 3. State Key Lab of Application Specific Circuits and Systems, Fudan University, Shanghai, China 4. Electrical and Computer Engineering Department, University of Alberta Email: feng07@ucla.edu; lhe@ee.ucla.edu Introduction Single Event Upset (SEU) Logic Masking SRAM-based Field Programmable Gate Arrays (FPGAs) are vulnerable to Single Event Upsets (SEUs). We show that a large portion (40%-60% for the circuits in our experiments) of the total used LUT configuration bits are don’t care bits, and propose to decide the logic values of don’t care bits such that Soft Error Rate (SER) is reduced. Our approaches are efficient and do not change LUT level placement and routing. Therefore, they are suitable for design closure. For the ten largest combinational MCNC benchmark circuits mapped for 6-LUTs, our approaches obtain 20% chip level Mean Time To Failure (MTTF) improvements, compared to the baseline mapped by Berkeley ABC mapper, which is 3× more improvements compared to the existing best in-place IPD algorithm. p+ p- n- n+ + - Sensitive Area VDD VSS 1 alpha+ I V R V=IR SEU 1 Not effected by the SEU! Observability Don’t-cares with a=1&b=1 Source neutrons coming from cosmic rays alpha particles emitting from trace impurities in packaging materials, solder bumps, etc. Impact Change the states of SRAM cells. Change the logic function and routing. SEUs are created equally but not propagated equally. Figure thanks to Joseph Fabula et al. Xilinx Motivation X-Filling Algorithm = SDC Our approach decides states of SDC bits in all LUTs to increase the likelihood of masking soft errors in the their fanin cones thereby to improve the reliability of the circuit. Assigning Satisfiability Don’t Care (SDC) bit to a different value does not change logic function, placement and routing, but it may reduce SER. In-Place Re-synthesis Flow Satisfiability Don’t Care Ratio Experiment Results LUT-Level Chip-level ABC IPF alu4 0.34 0.24 0.36 0.28 apex2 0.27 0.25 0.23 apex4 1.55 0.96 1.64 1.39 des 1.79 1.69 4.16 3.63 ex1010 1.21 1.13 1.62 1.43 exp5p 0.7 0.67 0.93 0.88 misex3 0.54 0.38 0.58 pdc 1.05 0.9 1.75 1.38 seq 0.66 0.52 0.73 0.59 spla 1.28 1.09 2.02 1.66 Failure Rate Ratio 1.00 0.83 MTTF Improvement 1.20 High-level circuit description Logic synthesis Logic optimization IPF Bitstream Physical synthesis Obtain 20% chip level MTTF improvements, compared to the baseline mapped by Berkeley ABC mapper, which is 3x more improvements when compared to the existing best in-place IPD algorithm. On average, 50.8% LUT bits are don’t cares when MCNC benchmark circuits are mapped to 6-input LUTs