Package Modeling Today

Slides:



Advertisements
Similar presentations
11 *Other names and brands may be claimed as the property of others Purpose –The following slides summarize rules and issues for the new mixed-mode format.
Advertisements

1 Introduction to VHDL (Continued) EE19D. 2 Basic elements of a VHDL Model Package Declaration ENTITY (interface description) ARCHITECTURE (functionality)
Package EBD/EMD Walter Katz IBIS Interconnect 11/13/12.
Package and On-Die Interconnect Decisions Made and Proposed Solutions Walter Katz IBIS ATM December 3, 2013.
IBIS-ISS Package Status Walter Katz IBIS ATM December 17, 2014.
IBIS Interconnect Decision Time Walter Katz IBIS Interconnect 6/19/13.
02/02/20091 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.
1/31/20081 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.
IBIS Interconnect BIRD Draft 3 Walter Katz Signal Integrity Software, Inc. IBIS Summit, DesignCon Santa Clara, CA January 30, 2015.
01/30/04 *Other brands and names are the property of their respective owners Page 1 Futures Subcommittee Proposed “New” Futures Subcommittee To create,
Signal Integrity Software, Inc.Electronic Module Description© SiSoft, 2008 Electrical Module Description EMD A new approach to describing packages and.
IBIS-AMI and Direction Indication February 17, 2015 Updated Feb. 20, 2015 Michael Mirmak.
IBIS-ISS Package Proposal Status Walter Katz IBIS ATM January 7, 2014.
Updated Interconnect Proposal Bob Ross, Teraspeed Labs EPEPS 2015 IBIS Summit San Jose, CA, October 28, 2015 Updated Interconnect.
DSD,USIT,GGSIPU1 Entity declaration –describes the input/output ports of a module entity reg4 is port ( d0, d1, d2, d3, en, clk : in std_logic; q0, q1,
Tutorial 1 Combinational Logic Synthesis. Introduction to VHDL VHDL = Very high speed Hardware Description Language VHDL and Verilog are the industry.
03/05/04 *Other brands and names are the property of their respective owners Intel Confidential Page 1 Original Cookbook Objectives Triage to find keywords.
IBIS-AMI and Direction Indication February 17, 2015 Michael Mirmak.
11/09/04 *Other brands and names are the property of their respective owners Page 1 The IBIS Specification and IEEE DASC Michael.
16- Agenda S-Parameters and Linear Analysis 4 Transmission Lines and Field Solver 5 IBIS 6 DAY 2 Synopsys 60-I-032-BSG-005 © 2007 Synopsys, Inc. All Rights.
Module 2.1 Gate-Level/Structural Modeling UNIT 2: Modeling in Verilog.
Package Modeling Status Walter Katz IBIS Open Forum December 6, 2013.
Updated Interconnect Proposal Bob Ross, Teraspeed Labs Draft Presented September 23, 2015 at the Interconnect Working Group Copyright.
Intel Confidential IBIS & ICM Interfacing: A New Proposal Michael Mirmak Signal Integrity Engineering Intel Corp. Chair,
IBIS & ICM Interfacing: Three Options Michael Mirmak Intel Corporation December 4, 2007.
(1) Basic Language Concepts © Sudhakar Yalamanchili, Georgia Institute of Technology, 2006.
8. Inheritance “Is-a” Relationship. Topics Creating Subclasses Overriding Methods Class Hierarchies Abstract Class Inheritance and GUIs The Timer Class.
Programming with Java © 2002 The McGraw-Hill Companies, Inc. All rights reserved. 1 McGraw-Hill/Irwin Chapter 5 Creating Classes.
06/02/04 *Other brands and names are the property of their respective owners Page 1 New IBIS Cookbook 1.0 Introduction.
Signal Integrity Software, Inc.Electronic Module Description© SiSoft, 2008 Electrical Module Description EMD A new approach to describing packages and.
Coming up: Inheritance
10/07/04 *Other brands and names are the property of their respective owners Page 1 IBIS & ICM Interfacing Options Alternative.
Updated Interconnect Proposal Bob Ross, Teraspeed Labs EPEPS 2015 IBIS Summit San Jose, CA, October 28, 2015 Updated Interconnect.
Pin Mapping Key Concepts From IBIS 6.0… “The [Pin Mapping] keyword names the connections between POWER and/or GND pins and buffer and/or terminator voltage.
IBIS & ICM Interfacing: Simple Link Michael Mirmak September 21, 2005.
IBIS Status and Future Direction Michael Mirmak Intel Corp. Chair, EIA IBIS Open Forum マイケル マ一マク インテル コ一ポレ一 ション 会長,アイビス JEITA IBIS Conference March 24,
Interconnect Terminal Mapping Figures 30 Sep
Fixing [Pin Mapping] Walter Katz Signal Integrity Software, Inc. IBIS Summit, DesignCon Santa Clara, CA January 22, 2016.
References in IBIS Bob Ross, Teraspeed Labs IBIS ATM Meeting January 12, 2016 Copyright 2016 Teraspeed Labs 1.
Simulation [Model]s in IBIS Bob Ross, Teraspeed Labs Future Editorial Meeting April 22, 2016 Copyright 2016 Teraspeed Labs 1.
[Die Supply Pads] Walter Katz Signal Integrity Software, Inc. IBIS Interconnect January 6, 2016.
IBIS Interconnect BIRD Draft 0 Walter Katz Signal Integrity Software, Inc. IBIS Summit, DesignCon January 27, 2015.
How to use S-parameter data files in ADS
Hardware Description Languages: Verilog
IBIS 6.2 Editorial Resolutions
V7.0 Linked BIRDs Bob Ross IBIS Editorial Task Group April 7, 2017
Basic Language Concepts
Walter Katz IBIS-ATM December 8, 2015
IBIS Interconnect Task Group December 15, 2015
Structural style Modular design and hierarchy Part 1
Chapter 3: Using Methods, Classes, and Objects
Hardware Description Languages: Verilog
IBIS [Model Selector] Improvement Proposal
The super Reference Constructors cannot be used in child classes, even though they have public visibility Yet we often want to use the parent's constructor.
Java Programming Language
Structural style Modular design and hierarchy Part 1
EGR 2131 Unit 8 VHDL for Combinational Circuits
Packages and Interfaces
IAY 0600 Digital Systems Design
CSSSPEC6 SOFTWARE DEVELOPMENT WITH QUALITY ASSURANCE
Interfaces.
Advanced Java Programming
IBIS Specification Roadmap
DUT vs DIA Device Under Test vs Device In Action
New IBIS Cookbook 1.0 Introduction 2.0 Pre-Modeling Steps
A QUICK START TO OPL IBM ILOG OPL V6.3 > Starting Kit >
Pin Reference Concerns Bob Ross, Teraspeed Labs
Ground Recommendations Review of Recent Discussion
IBIS 6.2 Editorial Resolutions
Presentation transcript:

Package Modeling Today |************************************************************************** [IBIS Ver] 3.2 [File name] example.ibs {...} [Component] Example_chip [Package Model] simple_package [Pin] signal_name model_name R_pin L_pin C_pin 1 IO1 io_buffer 2 IO2 io_buffer 3 IO3 io_buffer [Model] io_buffer Model_type I/O | [Define Package Model] simple_package [Number of Pins] 3 [Pin Numbers] A1 Len=1.2 L=2.0n C=0.5p R=0.05/ B1 Len=1.2 L=2.0n C=0.5p R=0.05/ C1 Len=1.2 L=2.0n C=0.5p R=0.05/ [End Package Model] [End] Header Pin/Model assignment Model definition Package Model definition/assignment

Package Modeling Today [Pin Numbers] IBIS 3.2 & 4.0 Approach If [Pin] and [Pin Numbers] use the same values… Tools assume connections corresponding to values Tools infer connections between [Model] and package [Model] [Package Model] [Pin] A1 implied! [Model] B1 implied! [Model] C1 implied!

Package Modeling Today A Few Oddities Package Pin attachment “A package stub description starts at the connection to the die and ends at the point at which the package pin interfaces with the board or substrate the IC package is mounted on.” A1 Len=0 L=1.2n/ Len=1.2 L=2.0n C=0.5p/ Len=0 L=2.0n C=1.0p/ Package Pins vs. Fork/Endfork “The package pin is connected to the last section of a package stub description not surrounded by a Fork/Endfork statements.” Pin is here!

? What about this? Forked t-line assignment This structure cannot be described using IBIS 3.2/4.0 Extra t-line can only be an unterminated stub [Pin Numbers] [Model] [Package Model] [Pin] A1 implied! [Model] ? [Model] C1 implied!

What do we need? The General Case… Need explicit link to [Model] instance [Model] [Pin] A1 [Model] B1 [Model] C1 Need explicit link to [Pin] instance

IBIS & ICM How can we use ICM to describe packages? Changes Required ICM can describe… interconnect RLGC or S-parameter characteristics coupling, if present, between interconnect segments pin (port) end-points and names ICM does not describe… connections between [Model], [Pin] and ICM end-points Changes Required IBIS: need explicit link between [Model] and [Pin] ICM can use node/pin map names from [Pin] listing [Model] link options listed below IBIS: explicit link between [E. Circuit] and [Pin]? [Node Declarations]! See below ICM: need differentiation between pin maps Currently, same pin map may be used for all end-points This is fixed in IIRD8 (Ross)

arbitrary packages not reusable IBIS & ICM Links Linking ICM to IBIS [E. Circuit] Use [Node Declarations] to list internal ICM map pin names Example: |**************************************** [Node Declarations] |Die pads A1, A2, A3, A4 [End Node Declarations] [ICM Pin Map] Example1_internal Pin_order Row_ordered Num_of_columns = 4 Num_of_rows = 1 Pin_list |Pin Name A1 AD2 A2 AD5 A3 AD7 A4 GND No spec. changes! Only downside: Names must be matched; arbitrary packages not reusable

IBIS & ICM Links Linking ICM to IBIS [Model] Options: This would cover [External Model] too Ultimate issues: [Model] ports have no names in 3.2/4.0 D_drive, etc. aren’t actually used except in 4.1 extensions Implied [Model] links exclude power supply connections to package information Need way to instantiate [Model] separately from [Pin] Careful! Could enable “floating” [Model] Options: New IBIS reserved word to separate [Model] from [Pin] Also a keyword; example: ICMLINK Similar to CIRCUITCALL in [Pin] [ICM LINK] would explicitly name ICM node/pin map, reserved port name, [Pin] name if any Extended to SPICE models/[External Circuit]s?

[ICM Link] Example Format resolves two issues Ugliness [ICM Link] package_model_name Signal_pin A1 | |Model_name instance port ICM_pin/node io_buffer1 1 A_signal CONN_A1 io_buffer1 1 A_pdref CONN_power io_buffer1 2 A_signal CONN_A2 io_buffer2 1 A_signal CONN_B1 [End ICM Link] Format resolves two issues Multiple [Model]s can now be linked with one ICM pkg Example: single pin with connection to two models Stubs and dangling structures can be included in ICM description without naming/connection in [ICM Link] Permits instantiation of multiple cases of the same [Model] Ugliness We have just bypassed/replaced [Pin]