PLL meeting 05/03.

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Presentation transcript:

PLL meeting 05/03

Triple redundant PFD

Progress PFD Charge pump Divider VCO Digital logic (FSM + programming) Layout done & verified Programmable resistor done Charge pump Divider Layout of individual blocks (%16 TMR , /2 CML) done & verified VCO Layout has to be updated to new size but verified old one Digital logic (FSM + programming) Done P&R Jitter 280fs RMS 1.2ps p2p 20-30 dB CMRR

To be done VCO buffer (level shifter) IO (Cern) PLL SEE counters Total layout Something else?

Input receiver Input as 40MHz sine wave Square wave Lot of jitter (3ps p2p) Due to low slew rate Square wave Generate with 700fs RJ (available @ Cern) Crystal oscillator