Question 8.18 (page 397) Design a digital system that multiplies two unsigned binary numbers by the repeated addition method. For example, to multiply.

Slides:



Advertisements
Similar presentations
Tutorial 2 Sequential Logic. Registers A register is basically a D Flip-Flop A D Flip Flop has 3 basic ports. D, Q, and Clock.
Advertisements

D Flip-Flop.
Counters Discussion D8.3.
Synchronous Counters with SSI Gates
Lecture 23: Registers and Counters (2)
1ASM Algorithmic State Machines (ASM) part 1. ASM2 Algorithmic State Machine (ASM) ‏ Our design methodologies do not scale well to real-world problems.
M. Mateen Yaqoob The University of Lahore Spring 2014.
Analysis of Clocked Sequential Circuits
//HDL Example 6-1 // //Behavioral description of //Universal shift register // Fig. 6-7 and Table 6-3 module shftreg.
Registers and Counters. Register Register is built with gates, but has memory. The only type of flip-flop required in this class – the D flip-flop – Has.
Multiplication Practice Do you know how to multiply with double digits?
Lab 10 RT methodology (cont’d) Example 1 – a counter Example 2 – a repetitive-adder multiplier.
Design example Binary Multiplier.
ENGIN112 L26: Shift Registers November 3, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 26 Shift Registers.
CS 140L Lecture 4 Professor CK Cheng 10/22/02. 1)F-F 2)Shift register 3)Counter (Asynchronous) 4)Counter (Synchronous)
Sequential Circuit Introduction to Counter
Asynchronous Counter © 2014 Project Lead The Way, Inc.Digital Electronics.
©2008 The McGraw-Hill Companies, Inc. All rights reserved. Digital Electronics Principles & Applications Seventh Edition Chapter 10 Arithmetic Circuits.
Asynchronous Counters with SSI Gates
Conversion Between Lengths Positive number pack with leading zeros +18 = = Negative numbers pack with leading ones -18 =
Multiplication by multiples of 10 and 100 Objective to multiply numbers when 0’s are involved.
Rabie A. Ramadan Lecture 3
Abdullah Said Alkalbani University of Buraimi
Anurag Dwivedi. Basic Block - Gates Gates -> Flip Flops.
Other Arithmetic Functions Section 4-5
Lecture 13 PicoBlaze I/O & Interrupt Interface Example of Assembly Language Routine ECE 448 – FPGA and ASIC Design with VHDL.
C OMPUTER A RITHMETIC. I NTRODUCTION A processor has an separate unit that is known as ALU that executes arithmetic operations. Negative numbers may be.
Counters and registers Eng.Maha Alqubali. Registers Registers are groups of flip-flops, where each flip- flop is capable of storing one bit of information.
Shift Register Counters
REGISTER TRANSFER AND MICROOPERATIONS
SERIAL MULTIPLIER Part 1
EKT 221 : DIGITAL 2.
CHAPTER 18 Circuits for Arithmetic Operations
Multiplying Decimals.
Homework Reading Machine Projects Labs Tokheim Chapter 9.1 – 9.6
REGISTER TRANSFER AND MICROOPERATIONS
SR Flip-Flop Negative Edge Triggered Flip-Flops The SR Flip-Flop
Chapter 4 Register Transfer and Microoperations
Asynchronous Counters with SSI Gates
Multiplying 2 Digit Factors
EKT 221 : Digital 2 COUNTERS.
Figure 12-13: Synchronous Binary Counter
Sequential Circuit: Counter
Principles & Applications
Even/odd parity (1) Computers can sometimes make errors when they transmit data. Even/odd parity: is basic method for detecting if an odd number of bits.
Principles & Applications
D Flip-Flop.
Shift Registers.
Digital System Design Review.
EEC 180B Lecture 14 Bevan M. Baas Tuesday, May 22, 2018
KU College of Engineering Elec 204: Digital Systems Design
Asynchronous Counters with SSI Gates
Multiplying Decimals.
Multiprocessor & Multicomputer
Computer Architecture and Organization: L11: Design Control Lines
FIGURE 10.1 Rectangular‐shape graphic symbols for gates
A.R. Hurson 323 CS Building, Missouri S&T
Number Systems and Circuits for Addition
Instructor: Alexander Stoytchev
ECE 3130 – Digital Electronics and Design
FIGURE 1: SERIAL ADDER BLOCK DIAGRAM
Digital Systems II EEC 180 Bevan M. Baas.
Switching Theory and Logic Design Chapter 5:
Digital Logic Department of CNET Chapter-6
Digital Logic Department of CNET Chapter-6
14 Digital Systems.
CHAPTER 18 Circuits for Arithmetic Operations
Forward Design by state transition table, and state graph
Computer Architecture
Presentation transcript:

Question 8.18 (page 397) Design a digital system that multiplies two unsigned binary numbers by the repeated addition method. For example, to multiply 5 by 4, the digital system adds the multiplicand four times: 5 + 5 + 5 +5 = 20. Let the multiplicand be in the register BR, the multiplier in register AR, and the product in register PR. An adder circuit adds the contents of BR to PR, and AR is down-counter. A zero detection circuit Z checks when AR becomes zero after each time that it is decremented. Design the control by the flip-flop per state method.

Tips : Start = 0 Z = 0 Start = 1 A B C Z = 1 Note : A, B, C – D flip-flops Z = 1 A : Initial state B : BR Input A AR Input B PR 0 C : PR BR + PR AR AR - 1 n LD BR LD n AR DEC n ADD 2n 2n Zero Z CLR PR LD

Answer : Q8-18 START LD_BR = LD_AR = CLR_PR LD_PR = DEC_AR Z B A C D D CLK RESET

Feedback: Privacy Policy Feedback
Do Not Sell My Personal Information
About project: SlidePlayer Terms of Service

© 2025 SlidePlayer.com. Inc. All rights reserved.