Digital Logic & Design Dr. Waseem Ikram Lecture 39

64-cell Memory Array 1 2 3 4 5 6 7 8 Row Column

Memory Organized as 4 x 16 and 1 x 64 Arrays 2 3 4 5 6 Row Column 13 14 15 16 61 62 63 64

Block Diagram of a Read-write Memory

Memory Read Operation

Memory Write Operation

Circuit diagram of a Static Memory Cell based on a flip-flop

3 x 8 Decoder DATA IN DATA IN DATA IN DATA IN 3 2 1 A2 A1 A0 OE OUT SEL WR 3 x 8 Decoder E N B DATA IN DATA IN DATA IN DATA IN 3 2 1 IN OUT SEL WR A2 A1 A0 W CS OE DATA OUT DATA OUT DATA OUT DATA OUT 3 2 1

16K x 8 Static RAM CS WE OE RAM A0 16K x 8 Address Lines Data Input/ Output Lines A13 CS WE OE

Recap ABEL Input file Controller circuit Equation Definition for timer reset Controller circuit ABEL file definitions for switching circuit Pin declarations Traffic lamp states Equation Definitions

Recap Analysis of Sync. State Machines Next State & Output functions Next State = F(Current State, Input) Output = G(Current State, Input) Construct State Table from functions F&G Draw State Diagram

Recap Characteristic Equation S-R flip-flop excitation/transition table S-R characteristic equation Kmap Other latches and flip-flops

Recap D/J-K-flip-flop based state machine ckt Finding Excitation inputs Finding transition equations Defining transition table O/p equation &Defining State Table State Diagram

Memory Memory Data Storage Memory Storage Latches and Flip-flops (small memory) Computer Program Memory (large memory) Data Storage Bits, Nibbles, Bytes, Words Memory Storage Storage array of cells (stores 0 or 1) Two dimensional array row & column (fig 1)

Memory Organization Memory Organization Memory Capacity and Density Byte Nibble (fig 2) Bit (fig 2) Memory Capacity and Density Memory Block diagram and Signals (fig 3) Address Data R/W and CS

Memory Memory Read Operation (fig 4) Memory Write Operation (fig 5) Memory Types RAM ROM RAM Types Static RAM implemented using flip-flops Dynamic RAM implemented using capacitors

Static RAM Structure Static RAM cell implementation (fig 6) Internal structure of 8 x 4 RAM (fig 7) 16K x 8 RAM chip (fig 8)