COMPERE Project Meeting Dr Dawei Xiang 03/11/2008

Contents IGBT terminal characteristics simulation VSI characteristic harmonics simulation Problems IV. Further work plan ESR Network

IGBT terminal characteristics simulation ESR Network

Aims of study To build a detailed simulation model for understanding the fundamentals of device operation and analysis of device Failure Modes and Mechanisms and their effects (FMMEA). To form a basis for power converter terminal characteristics study and CM method research. ESR Network

IGBT degradation and its effects Devices are subjected to interrelated thermal, electrical and mechanical stresses. Failure locations Failure causes Failure mechanisms Failure effects Die-attach solder temperature swings Different CTEs Thermal gradients Active area (A), Thermal resistance (Rjc) Temperature (T) Gate oxide High temperature High electric field Over voltage High current density Time dependant dielectric breakdown Hot electrons Mosfet channel threshold voltage (Vt) Mosfet channel transconductance (Kp) FMMEA analysis of IGBT ESR Network

Saber physic-based IGBT model Hefner IGBT model Advantages: Detailed physic model Electrothermal simulation available Experimentally verified Disadvantages: Difficult to parameterize Encryption of MAST template ESR Network

Case study Considering a IGBT under the stresses caused by high temperature and high current, the effects of die-attach solder fatigue and/or gate oxide degradation are simulated by artificially changing the corresponding parameters in the Saber physics-based IGBT model. Case 1 Case 2 Case 3 Case 4 Case 5 degraded parameters T↑: 27°=>50° A↓33% Vt↑10% Kp↓10% A↓, Vt↑, Kp↓, T↑ Combinations of IGBT parameters to simulate the solder fatigue and/or gate oxide degradation IGBTs: hgtg27n120bn (1200V/27A) ESR Network

Simulated circuits DC characteristics analysis circuit dynamic characteristics analysis circuit ESR Network

Simulation results (case 1: T↑) a) Ic-Vge Vge(th): no effect gfs: 130 S=>143 S (↑10%) b) Ic-Vce For Vge=11V Vce0:1.25V=>0.9V (↓28%) Ron: 0.05Ω=>0.015Ω (↓70%) ESR Network

Simulation results (case 1: T↑) c) Turn on td(on): no effect tr: no effect d) Turn off td(off): 300ns=>200ns (↓33%) trv: 150ns=>500ns (↑233%) tf1: no effect Itail0: 2A=>12A (↑500%) tf2: 0.8us=>5us (↑525%) ESR Network

Simulation results (case 5) a) Ic-Vge Vge(th): 8 V=>8.6 V (↑7.5%) gfs: 130 S=>106 S (↓18.4%) b) Ic-Vce For Vge=11V Vce0: 1.25V=>0.9V (↓28%) Ron: 0.05Ω=>0.027Ω (↓46%) ESR Network

Simulation results (case 5) c) Turn on td(on): 97 ns=>113ns (↑6%) tr: no effect d) Turn off td(off): 300ns=>200ns (↓33%) trv: 150ns=>400ns (↑166%) tf1: no effect Itail0: 2A=>8A (↑300%) tf2: 0.8us=>1.8us (↑125%) ESR Network

Simulation results (case 2: A↓) Fault detection based on gate voltage Monitoring [1] Simulated turn on transient [1] M. Rodriguez, A. Claudio, D. Theilliol et al., “A new fault detection technique for IGBT based on gate voltage monitoring,” in IEEE Power Electronics Specialists Conference, 17-21 June 2007, pp. 1001-1005. ESR Network

Results and discussions IGBT terminal characteristics affected by aging (NE: No Effect) Characteristics Aging parameters VGE(th) gfs VCE0 Ron td(on) tr td(off) trv tf Case 1: T↑ NE ↑ ↓ Case 2: A ↓ Case 3: Vt↑ Case 4: Kp↓ Case 5: A↓, Vt↑, Kp↓, T↑ ESR Network

Results and discussions Temperature influences the carrier mobility, high-level lifetime, which leads to the changes of device DC and dynamic characteristics. Reduced die-attach area increases the base resistance so as to the total on-state resistance, while the turn-on transient is affected by the Agd so as to the Cgdj. The tapped electrons in gate oxide reduces the Vt, which influences the DC characteristics and the dynamic delay times: td(on) and td(off). The gate oxide degradation influences the transconductance which can mainly be reflected on the device DC characteristics. Case 5 illustrates the combined aging effects caused by the solder fatigue and gate oxide degradation. Simulation results show there exists the change of device terminal characteristics due to aging, which can be used for CM. ESR Network

II. VSI characteristic harmonics simulation ESR Network

Aims of study To investigate the effect of the devices aging on the power converter characteristic harmonics. To form a basis for the study of harmonic resonance based power converter CM method. To built a simulation model to investigate other power converter terminal characteristics affected by device aging, eg. EMI characteristics. ESR Network

Origin of characteristic harmonics Origin of characteristics harmonics in one phase PWM voltage waveforms for positive current ESR Network

Simulated 3-phase VSI in Saber Case study Simulated 3-phase VSI in Saber DC link voltage: Vdc=600V Gate circuit parameters: Rg=12 Ω, lg=100nH Switching frequency: fsw=10 kHz Dead time: td=2μs Carrier frequency: fc=50 Hz Modulation ratio: M=0.8 IGBT: hgtg27n120bn (1200V/27A) Diode: hf50d120ace (1200V/50A) Load inductance: Ll=0.8867 mH Load resistance: Rl=10 Ω The same 5 cases as previous were simulated where the IGBT parameters are changed to simulate the solder fatigue and/or gate oxide degradation ESR Network

Simulation results (case 1: T↑) Spectrum of phase A current for 3-phase VSI before and after aging (T increasing) ΔU5th= ΔI5th*Z5=(0.17066-0.22982)*10.0965=-0.5973 V ΔU7th= ΔI7th*Z7=(0.086418-0.11926)*10.1883=-0.3346 V ESR Network

Results and discussions Characteristics harmonics affected by aging Harmonics Aging parameters ΔV5th (V) ΔV7th (V) Case 1: T↑ -0.5973 -0.3346 Case 2: A ↓ 0.0158 0.0110 Case 3: Vt↑ 0.0351 0.0288 Case 4: Kp↓ 0.0024 0.0047 Case 5: A↓, Vt↑, Kp↓, T↑ -0.2921 -0.2045 ESR Network

Results and discussions The IGBT Vce0 and switching behavior determines the amplitude of characteristic harmonics through changing the V-A characteristics of output PWM voltage during aging. Simulation results show that characteristics harmonics are more sensitive to the changes of temperature while the other factors may have slight effects on them. Under the predefined simulation conditions, a deviation of about 0.3V can be reached for 5th harmonic. Such a variation falls in the range where our previous harmonic resonance method is capable of detecting. ESR Network

III. Problems ESR Network

Problems Power electronics modelling and simulation As Saber model is difficult to be parameterized, which can be solved by using Angus’s devices model. And there comes the problems of obtaining the permission of this model for the research of the project. Conflicting results of IGBT characteristics degradation Our simulation results show that Ron decreases with the rise in temperature because of the negative temperature coefficient of resistance for p-n junction [2]. While some literatures reported an increase of Vce(sat) after aging which was explained by the consequence of increased channel resistance [3]. [2] Nishad Patil, Diganta Das, Kai Goebe and Michael Pecht, “Failure Precursors for Insulated Gate Bipolar Transistors (IGBTs),” 2008. [3] Maiga, C.O. Tala-Ighil, B. Toutah, H. Boudart, B., “Behaviour of punch-through and non-punch-through insulated gate bipolar transistors under high temperature gate bias stress”, IEEE International Symposium on Industrial Electronics, 2004, pp.1035- 1040 ESR Network

IV. Further work plan ESR Network

Terminal characteristics simulation More simulations will be carried out to further study the terminal characteristics of device and converter under different conditions, eg. working point, ambient temperature and unbalanced operation. Electrothermal simulations will be carried out in order to take the device self-heating effect in to account. Detailed analysis will be made systematically to correlate the characteristics changes to the device conditions. ESR Network

Accelerated aging test Over loading the IGBT by DC power supply for 1 hour to simulate a long period conduction stress operation.[4] Regulating the gate voltage to allow case temperature to be increased up to 155°C [4] A. Maouad, A. Hoffmann, A. Khoury, J.-P. Charles, “Characterization of high-density current stressed IGBTs and simulation with an adapted SPICE sub-circuit,” Microelectronics Reliability, 40, 2000, pp. 973-979. ESR Network

Accelerated aging test Accelerated power cycling test system [5] It normally takes 2-3 months to complete an aging test of approx. 600,000 cycles [5] Xiong Y., Cheng X., Shen Z.J., Mi C., Wu H., Garg V., “A Prognostic and Warning System for Power Electronic Modules in Electric, Hybrid, and Fuel Cell Vehicles”, IEEE Industry Applications Conference, Oct. 2006, pp.1578 – 1584. ESR Network

Experimental verification on drive system Rating: 400V /10kW ESR Network

New CM studies On-state resistance identification based CM DC offset identification based CM EMI characteristics based CM low frequency characteristics high frequency characteristics ESR Network

Initial idea for Ron identification Synchronous machine: 460V/ 60Hz/ 200HP Rs=2.01 mΩ Ψs_transient decays during Us sudden drop from 1pu to 0.95pu ESR Network

Thanks for you attention!