Update on Bump Bonding GTK-Meeting Sep. 2, 2008 pr

Phone meeting with VTT 6/8/2008 (Michael, Petra) Prepared a set of questions as collected before (Flavio, Jan, Pierre, …) Mainly concerning sensor design GTK-Meeting Sep. 2, 2008 pr

Sensor Edge Design How far from the active pixel cell can the dicing lane be placed Question needs to be re-discussed with FBK (depends on wafer doping, etc.) VTT recommendation: at least 560 µm between last active pixel and centre of dicing lane ; reserve 100 µm between sensors for dicing; GTK-Meeting Sep. 2, 2008 pr

Arrangement of Structures on the Sensor Wafer VTT recommendation: place prototype chips such that they do not interfere with large sensor dicing; do not place metal on dicing lanes; minimize the number of cuts; wafer large sensor 5 x 2 chips GTK-Meeting Sep. 2, 2008 pr

Placement of Chips on Final Sensor How big should the distance between diced chip edges be? Is the “dynamic bump position” on the sensor a problem? What should be the minimum distance of the bump wrt the active edge of the cell on the sensor? VTT recommendation: leave at least 100 um between chip edges; “dynamic bump position” poses no problem; Keep at least 30 µm between the pixel metallisation edge and the bump pad center; GTK-Meeting Sep. 2, 2008 pr

Bump Pad Size Assuming an octagonal pad (ALICE, Medipix, …) what is the preferred bump pad size and bump size. Taking into account that the MOSIS run will have a 3-5 µm polyimide passivation. VTT recommendation: preferred passivation opening: 20 µm, bump diameter: 30 µm. GTK-Meeting Sep. 2, 2008 pr

Bump Transfer Method proposed for prototype chips Protection of the wire bonding pads during the UMB (under bump metallisation) and wettable metal deposition still needs to be worked out in detail. Further discussions with VTT needed GTK-Meeting Sep. 2, 2008 pr