Activity report of FoCAL from CNS 1 Activity report of FoCAL from CNS Taku Gunji Hideki Hamagaki, Yasuto Hori, Tomoya Tsuji ShinIchi Hayashi, Atsushi Nukariya Center for Nuclear Study University of Tokyo FoCAL Meeting on 6/24/2010

Outline Status of simulation efforts Status of hardware efforts 2 Outline Status of simulation efforts Status of hardware efforts Conceptual design of readout flow Conceptual design of Frond-End-Electronics R&D of ASIC dual preamplifier at RIKEN Preliminary performance and future plans Discussion on FoCAL trigger

3 Simulation Efforts Basic detector performances and p0 reconstruction have been studied by Yasuto. His thesis in the Twiki page. https://twiki.cern.ch/twiki/bin/view/ALICE/FoCALLinks Our preliminary detector design: W thickness: 3.5 mm Si pad size: 1.1x1.1cm2 Si wafer size: 9cm x 9cm # of pads/wafer: 64 Si thickness 0.5 mm W+Si pad : 21 layers Strip readout: 0.5 – 1 mm pitch One tower

4 Recent works and plan Tomoya took over Yasuto’s work and started (or will start) following studies (with me…). Limitations of the dead space between towers Dilution of the performances is under investigation Necessary information for the mechanics Implement response from readout electronics Implementation in AliFoCALDigits (0.5 month) Full simulation with current our detector design Start with p+p (1 month) and p+A (1.5 month)

5 Hardware efforts 4 silicon pads ($XXXX/pad) were delivered to CNS from Hamamatsu. QA was done by Hamamatsu.

Cd & Id vs. V Cd and Id characteristics vs. V. 6 Cd & Id vs. V Cd and Id characteristics vs. V. Typ: Cd=25(center)-30pF(edge), Id=2(center)-10pA(edge) Depletion voltage : 100V

Data Flow from pads-I STU/TOR 7 wafer (64 pads) 3 longitudinal segments 7 layers/segments One wafer contains 64 pads. wafer size: 9cm x 9cm x 0.5 mm pad size: 1.1 x 1.1cm x 0.5mm Signal bus driving 64 x 3 channels . Design under discussion Transition card FEE card (64channel/card) 4 ACIS ‘s(preamplifier + shaper, analog sum for trig.) 8 ALTRO’s (FADC +filter + multi event buffering) GTL bus STU/TOR CTP TRU card (L0/L1 generation) 2x2 pad sum signal input fast shaping and FADC 4x4 sum/comparator (FPGA) DCS RCU LTU DCS TRU/RCU/FEE cards used in EMCAL/PHOS can be useful for us!! LDC GDC

Data Flow from pads-II STU/TOR 8 wafer (64 pads) 3 longitudinal segments 7 layers/segments One wafer contains 64 pads. wafer size: 9cm x 9cm x 0.5 mm pad size: 1.1 x 1.1cm x 0.5mm ASIC preamp+shaper card FEE card (64channel/card) 8 ALTRO’s (FADC +filter + multi event buffering) GTL bus STU/TOR CTP TRU card (L0/L1 generation) 2x2 pad sum signal input fast shaping and FADC 4x4 sum/comparator (FPGA) DCS RCU LTU DCS TRU/RCU/FEE cards used in EMCAL/PHOS can be useful for us!! LDC GDC

Data Flow from pads-III 9 wafer (64 pads) 3 longitudinal segments 7 layers/segments One wafer contains 64 pads. wafer size: 9cm x 9cm x 0.5 mm pad size: 1.1 x 1.1cm x 0.5mm Signal bus driving 64 x 3 channels Transition card Preamp+shaper board (4 ASIC’s) FEE card (64channel/card) 8 ALTRO’s (FADC +filter + multi event buffering) GTL bus STU/TOR CTP TRU card (L0/L1 generation) 2x2 pad sum signal input fast shaping and FADC 4x4 sum/comparator (FPGA) DCS RCU LTU DCS TRU/RCU/FEE cards used in EMCAL/PHOS can be useful for us!! LDC GDC

Data Flow from pads-IV 10 wafer (64 pads) 3 longitudinal segments 7 layers/segments One wafer contains 64 pads. wafer size: 9cm x 9cm x 0.5 mm pad size: 1.1 x 1.1cm x 0.5mm Signal bus driving 64 x 3 channels Transition card Preamp+shaper board (4 ASIC’s) Output is driven by the cable to FEE card FEE card (64channel/card) 8 ALTRO’s (FADC +filter + multi event buffering) Somewhere near the detector

Global view for readout 11 Global view for readout Global view for readout architecture example: Mechanics for support has not been considered.

Readout using ALTRO&RCU 12 Readout using ALTRO&RCU ALTRO readout system (FEE-GTL-RCU) are quite well established for TPC/PHOS/EMCAL (ILC-TPC/STAR-TPC). It is worthwhile to consider using ALRTO system for FOCAL. Some concerns for FOCAL: Data size/Bandwidth In central p+Pb collisions, the particle density (charged + g) is 5%/cm2 This means that the occupancy could be 2.5%+2.5%*10(3x3)= 30%. If we take 25 samples (15 pre-sample + 10 sample after L0, 10 bit FADC), data size from FOCAL could be: 0.3*256(towers)*64*3(ch/tw)*25(samples)*2(L/H gain)*10(bit)~ 920kB/evt (TPC~2MB/evt, TRD~400kB/evt…). For GTL bus, 920kB/evt/32(RCU)=30kB/evt. If we require photon pT>0.5 (threshold), multiplicity decrease by a factor of 10. Event rate in this case could be ~1kHz.  GTL bus rate: 30MB/s < 100MB/s (MAX) To cope with the ALTRO with 15(pre)+10 samples 10MHz ADC clocks (20MHz is disfavored due to L0 latency~800nsec). 100nsec peaking time for preamp+shaper like EMCAL. (How we see noise??)

Readout electronics Requirements for us: 13 Readout electronics Requirements for us: Dynamic range: 1.2MeV(50fc)(MIP) – 5GeV(200pC)(20GeV@h=4) S/N = 10 for MIP, cross talk <1% Peaking time=100nsec for shaper, differential output [-1, 1]V For example, readout electronics of EMCAL and PHOS PHOS: 5MeV-80GeV (16000), EMCAL:16MeV-250GeV (16000) CSP  Dual gain Shaper (CR-RC2)  Differential driver  FADC CR-RC2 shaper (dual integrator) & differential driver [H/L gain]

Our plan for Readout electronics 14 Our plan for Readout electronics Dual CSP + Shaper (CR-RC2) with Differential driver + FADC FADC Shaper + Differential driver High Pads P-Z Low P-Z Clow<Chigh One example & concerns: input : 50fc – 200pC if we use 20pF as feedback high side : 2.5mV(50fc) – 250mV(5pc) Low side: 10mV(2pC) – 1V(200pC) If we use ALTRO (10bit, [-1,1V]) different shaper gain (x4, x1) resolution might be problem in low side? We need more bits? Dual gain shaper for low side? log Qin log Vout High Low

R&D of ASIC Dual CSP C high C low 15 R&D of ASIC Dual CSP Purpose is to achieve large dynamic range (~10000) Collaboration with RIKEN group RIKEN will use this dual amp to measure dE/dx of proton & heavy ions (Z<50) in silicon with strip readout. (228mm pitch) Their target range : 10fc -25pC (0.2MeV – 0.5GeV) Capacitive division: Clow = Chigh/10 Large open loop gain for amplifier is needed. Z = 1/C + Zf/A C low C high 1.8pF (RIKEN ) A = 10000 High gain 1.8pF (RIKEN) Qin Low gain

Current results Chigh Clow 16 Chip size 1 mm ×2 mm One channel for H/L. 20mW/ch 0.5 mm pitch lead SA(high gain) Chigh 7 mm Clow SA(low gain) 7 mm Qin (fC) 6 (= 136 keV) 12 18 Noise FWHM~90keV (S/N=10@MIP) Linearity : 10000 0.15 MeV – 1.5GeV

Next R&D plan Next R&D plan RIKEN CNS 17 Next R&D plan Next R&D plan RIKEN Check more characteristics (cross talk, source of the noise ) Now one chip contains 1ch (low/high) and implement more channels in the chip (~16 ch in final). Improvement of the linearity (especially around saturation regime) CNS Optimize to our purpose (Chigh, Clow, CF, RF,,) with inclusion of the noise study (series/parallel noise) Implement shapers with differential output in ASIC and Another candidate (trans-impedance amp as preamp) Next version will be available around August.

18 FoCAL Trigger Let’s discuss the possible scenario for the FoCAL trigger For the study of CGC, physics associated with small-x and smaller Q2 might be interesting. Direct photons/pi0-jet correlation What FoCAL triggers for what? Single photons (isolation?) pi0-jet trigger in conjunction with the central barrel How beneficial of the trigger? Event rejection Need to do quantitative simulations/calculations

Basic parameters Basic parameters for inputs 19 Basic parameters Basic parameters for inputs http://cdsweb.cern.ch/record/689223/files/INT-1997-13.pdf?version=1 Pi0 and direct photon production cross section in p+Pb and p+p Expected rate (p+p): Inelastic collisions ~40kHz pi0 (pt>2GeV, h=3-4) ~200Hz rejection=200 Expected rate (p+A) ~200kHz Pi0 (pt>2GeV, h=3-4) ~4kHz rejection=50 eta=3-4 eta=3-4 Direct photon p+p@8TeV p+Pb@8TeV p+p@8TeV Decay photon Pi0, g from pi0 Annual Year yield (DAQ efficiency not included)

Hardware for FoCAL Trigger 20 Hardware for FoCAL Trigger More detail will be determined according to quantitative studies by simulations. Possible scenario for the trigger logic. As EMCal/PHOS are doing, take 2x 2 analog sum, digitize 2x2 analog sum and take 4x4 sliding summation. In terms of the multiplicity, particle density in central p+A collisions is 0.04/cm2. This means 1 particle per 5x5 cm2. 8 x 8 summation might be disfavored. 2x2 or 4x4 might be the candidate. Longitudinal summation in the bus. TRU FADC (40MSPS) ALTRO ASIC 32 4 32 4 Fast shaper 32 FPGA 64 4 32 4 L0/L1 V->I 2x2 sum 16ch