Recall Last Lecture Common collector Voltage gain and Current gain Gain is positive Output resistance, Ro

COMMON EMITTER GROUNDED Independent voltage source turned off vbe = 0 V since there is no voltage supply attached to the input side so, gmvbe = 0  a zero current source means open circuit 6 k 105.37 k Hence, Ro = the parallel equivalent resistance = 5.677 k

so, ib = 0  a zero current source means open circuit COMMON EMITTER WITH RE Vx Ix Independent voltage source turned off ib = 0 A since there is no voltage supply attached to the input side to supply the current so, ib = 0  a zero current source means open circuit Vx Ix Hence, Ro = 6 k 6 k 0.6 k

AMPLIFIER INPUT RESISTANCE, Ri OUTPUT RESISTANCE, RO Common Emitter Equivalent to Ri as in the steps to find voltage gain Equivalent to Rout as in the steps to find voltage gain Common Collector Use the formula or find Ro using test voltage, Vx with current Ix.

Chapter 6 The Field Effect Transistor

MOSFETs vs BJTs MOSFETs BJTs Mostly widely used today Low power Very small device (nm) Simple manufacturing process Only 1 current, ID BJTs Three different currents in the device: IC, IB and IE Consume a lot of power Large size device

MOS Field Effect Transistor In the MOSFET, the current is controlled by an electric field applied perpendicular to both the semiconductor surface and to the direction of current. The phenomenon is called the field effect. The basic transistor principle is that the voltage between two terminals, provides the electric field, and controls the current through the third terminal. metal oxide substrate

Two-Terminal MOS Structure A MOS capacitor with a p-type semiconductor substrate: the top metal terminal, called the gate, is at a negative voltage with respect to the substrate. A negative charge will exist on the top metal plate and an electric field will be induced. If the electric field penetrates the semiconductor, the holes in the p-type semiconductor will experience a force toward the oxide-semiconductor interface and an accumulation layer of holes will exist

Two-Terminal MOS Structure The same MOS capacitor, but with the polarity of the applied voltage reversed. A positive charge now exists on the top metal plate and the induced electric field is in the opposite direction If the electric field penetrates the semiconductor, holes in the p-type material will experience a force away from the oxide-semiconductor interface.

Two-Terminal MOS Structure As the holes are pushed away from the interface, a negative space-charge region is created. This region of minority carrier electrons is called an electron inversion layer. The magnitude of the charge in the inversion layer is a function of the applied gate voltage, hence the larger voltage is applied, the wider it becomes

NMOS Enhancement Mode Transistor Structure The gate, oxide, and p-type substrate are the same as those of a MOS capacitor. There are two n-regions, called the source and drain terminal. The current in a MOSFET is the result of the flow of charge in the inversion layer, called the channel region, adjacent to the oxide-semiconductor interface.

NMOS Enhancement Mode If a large enough positive voltage gate voltage is applied, an electron inversion layer connects the n-source to the n-drain. A current can then be generated between the source and drain terminals. Since a voltage must be applied to the gate to create the inversion charge, this transistor is called an enhancement mode MOSFET. Since the carriers in the inversion layer are electrons, this device is called an n-channel MOSFET (NMOS).

Ideal MOSFET Current-Voltage Characteristics – NMOS Device The threshold voltage of the n-channel MOSFET, denoted as VTH or VTN, is defined as the applied gate voltage needed to create an inversion charge. If the VGS < VTN, the current in the device is essentially zero. If the VGS > VTN, a drain-to-source current, ID is generated as an induced electron inversion layer / channel is created

Ideal MOSFET Current-Voltage Characteristics – NMOS Device holes experience force same direction of electric field, leaving an electron inversion layer Direction of Electric field A positive but small drain voltage, VDS creates a reverse-biased drain-to-substrate pn junction, depletion region width increases At the drain end, the inversion layer bridges the depletion region, providing a path for the current to flow. So current flows through the channel region, not through a pn junction.

Reverse-Biased pn Junction There is an increase of the electric field in the depletion region, the number of charges increases too since the width of the depletion increases. ++ - - W E p n Equilibrium ++ - - - - ++ ET p n Reverse Biased WR

Ideal MOSFET Current-Voltage Characteristics – NMOS Device The iD versus vDS characteristics for small values of vDS When vGS < VTN, the drain current is zero. When vGS > VTN, the channel inversion charge is formed and the drain current increases with vDS With a larger gate voltage, a larger inversion charge density is created, and the drain current is greater for a given value of vDS

Ideal MOSFET Current-Voltage Characteristics – NMOS Device In the basic MOS structure for vGS > VTN with a small vDS: The thickness of the inversion channel layer qualitatively indicates the relative charge density. Which for this case is essentially constant along the entire channel length.

VGS VDS S G D - - - - - - - - - - - - - - - - - - - - - - - - - + - VGD VGS = VG – VS VGD = VG – VD But VGD = VGS – VDS VGD = VG – VS – VD +VS So, if VDS is small, VGD VGS, we have approximately equal distribution of channel inversion layer

Ideal MOSFET Current-Voltage Characteristics – NMOS Device VGD = VGS – VDS When the drain voltage vDS increases, the voltage drop across the oxide near the drain terminal decreases – no longer uniform distribution. It means that the induced inversion charge density near the drain also decreases. It causes the slope of the iD versus vDS curve to decrease.

VGD = VGS – VDS sat VDSsat = VGS - VTN As VDS increases, the channel at the drain end reaches the pinch-off point and the value of VDS that causes the channel to reach this point is called saturation voltage VDSsat VGD = VGS – VDS sat At the pinch off point, VGD = VTN VGD = VGS – VDS sat VTN = VGS – VDS sat Hence, VDSsat = VGS - VTN

Ideal MOSFET Current-Voltage Characteristics – NMOS Device When vDS becomes larger than vDS(sat), the point in the channel at which the inversion charge is zero moves toward the source terminal. In the ideal MOSFET, the drain current is constant for vDS > vDS(sat). This region of the iD versus vDS characteristic is referred to as the saturation region. The electrons travel through the channel towards the drain but then they are swept by the electric field to the drain contact

Ideal MOSFET Current-Voltage Characteristics – NMOS Device The region for which vDS < vDS(sat) is known as the non-saturation or triode region. The ideal current-voltage characteristics in this region are described by the equation: Kn = conduction parameter

Ideal MOSFET Current-Voltage Characteristics – NMOS Device In the saturation region, the ideal current-voltage characteristics for vGS > VTN are described by the equation:

LIST OF FORMULAS: NMOS VDSsat = VGS - VTN TRIODE OR NON-SATURATION REGION SATURATION REGION VDSsat = VGS - VTN and Where

Circuit Symbols and Conventions – NMOS FET is a voltage controlled device meaning the voltage VGS determines the current flowing, ID

PMOS Enhancement Mode Transistor Structure The substrate is now n-type and source and drain areas are p-type. The channel length, channel width, and oxide thickness parameter definitions are the same as those for NMOS device. Cross section of p-channel enhancement-mode MOSFET

Except the hole is the charge carriers rather than the electron. Basic PMOS Operation The operation of the p-channel device is the same as that of the n-channel device. Except the hole is the charge carriers rather than the electron. A negative gate bias is required to induce an inversion layer of holes in the channel region directly under the oxide. Direction of Electric Field Electrons experience force opposite direction of electric field, leaving a hole inversion layer

The threshold voltage for the p-channel device is denoted as VTP Since the threshold voltage is defined as the gate voltage required to induce the inversion layer, for PMOS, VTP is a negative value Once the inversion layer has been created, the p-type source region is the source of the charge carrier so that holes flow from the source to drain.

Ideal MOSFET Current-Voltage Characteristics – PMOS Device The ideal current-voltage characteristics of the PMOS device are essentially the same as those as the NMOS device, but the drain current is out of the drain and vDS is replaced by vSD The saturation point is given by vSD (sat) = vSG + VTP For the p-channel device biased in the non-saturation (triode) region, the current is given by: In the saturation region, the current is given by:

Circuit Symbols and Conventions – PMOS Enhancement mode

LIST OF FORMULAS: PMOS VSG > |VTP | VSDat = VSG +VTP TRIODE OR NON-SATURATION REGION VSG > |VTP | SATURATION REGION VSDat = VSG +VTP and Where

PMOS NMOS VTP is NEGATIVE VTN is POSITIVE VSG > |VTP| to turn on Triode/non-saturation region Saturation region VSDsat = VSG + VTP NMOS VTN is POSITIVE VGS > VTN to turn on Triode/non-saturation region Saturation region VDSsat = VGS - VTN