ETD/Online Report D. Breton, U. Marconi, S. Luitz WS goals session – Annecy Meeting March 16th 2010 D. Breton - SuperB Annecy Workshop - March 2010

Highlights from Frascati workshop In Frascati, we had a very fruitful meeting and converged onto a lot of elements of the architecture: the fact of having a fully triggered system, including the calorimeter the trigger primitives will be sent to the trigger processors through the same synchronous Gbit/s links as those used for clock and control distribution there we take advantage of the bi-directional chipset and mezzanine under development at Napoli the granularity of the EMC trigger towers (also optimized to feed the above-quoted synchronous links) Towers of 25 crystals for the forward => 4 towers per trigger link Towers of 12 crystals for the forward => 6 towers per trigger link the number of readout links Total number of ~330 links is very reasonable the granularity of the ROM system: 1 crate per sub-detector would be necessary This would allow to ensure an easy partitioning of the system 8 links per ROM looks appropriate (16 Gbits/s input rate) This number has to be studied in accordance with the smaller data compression ratio of all subsystems D. Breton - SuperB Annecy Workshop - March 2010

What was done since Frascati workshop Based on these decisions, our main activities of the last months as defined at Frascati were as for everybody else: the writing of the white paper ETD/Online sections the building of the ETD/Online budget document This work was driven by the ETD/Online conveners With the contribution of all the subsystem contact persons and conveners for everything concerning the FEE (WP and budget) This was an heavy but very useful job Not obvious to obtain a homogeneous content and style from so many different sources Putting things on paper pushes people to clarify their ideas Lots of interesting questions raised, often triggering long e-mail exchanges Implementation of subdetector specific FEE Interface with common FEE Effects of trigger rate, trigger window length and minimal distance between triggers D. Breton - SuperB Annecy Workshop - March 2010

Points to think of for the parallel sessions (1) In BABAR, dead-time (2.7µs) was introduced in the FCTS system after a level 1 trigger decision in order to simplify the front-end. this was not a problem because of the reasonable luminosity and low trigger rate (3kHz) In SuperB, at 150kHz, this would be an important source of dead-time The question remains: do we just leave the door fully open and put no restriction on the trigger ? Minimum distance between triggers would be only due to the trigger processors capacity to distinguish between consecutive events ~ 100ns The queue of previous events might be present in the following ones filtering this is a good job for the ROMs If the distance is smaller than the readout window, we’ll have to share the information between consecutive events (pile-up). we already showed that this is feasible in the common FEE recovering from pile-up is another good job for the ROMs D. Breton - SuperB Annecy Workshop - March 2010

Points to think of for the parallel sessions (2) Safety factors on dataflow: We would like to get the safety factors used for the readout link calculations for each subsystem and to understand what they are based on. Subsystems shouldn’t apply general safety margins like that on trigger rate => that one will be common to the whole experiment But they should for what concerns their channel occupancy (based on channel hit rate and trigger window width) Derandomizer depth: Should we ensure that no data could be lost after throttling in the derandomizer buffer even in the case of worst size events ? ECS bandwidth: Subdetectors should think of the bandwidth they need to set up the FEE at startup or reload it because of radiation policy Set up time has to be reasonable (seconds) This is a key factor in defining the number of ECS links needed (10Mbits/s per links) D. Breton - SuperB Annecy Workshop - March 2010

Main subjects for this workshop Work went ahead on the FCTS design We concentrated on the different possible uses of ATCA crates Should we use custom links on an ATCA backplane, or ATCA itself ? Should we use ATCA motherboards for FCTM or custom boards ? FPGA-based Ethernet interface for ECS field bus masters is now running This is currently being developped for LHCb Ethernet interface is an IP from Altera Work is going on in Napoli concerning the radiation qualification of the different links This is a crucial point for the validation of a commercial chipset A preliminary study of the Front-End Control coding for SuperB serial links has been launched: This is a very important feature for the reliability of the clock and control distribution R&D is starting on implementing the UDP protocol on a FPGA to be used as ROM's output stage toward the PC farm This is a outstanding R&D. D. Breton - SuperB Annecy Workshop - March 2010

D. Breton - SuperB Annecy Workshop - March 2010 Electronics costing EDIA Labor M&S TOTAL WBS Item (MM) (K$) (Keuro) 1.7 Electronics 994 18877 13103 342 6498 4511 10601 7359 35976 24973 1.7.1 SVT 11,0 Cost of SVT electronics estimated by Mauro 21,0 468 1.7.2 DCH 74 Cost of DCH electronics estimated by Giulietto 76 1390 1.7.3 PID Barrel (32k channels) 136 Cost of PID Barrel electronics estimated by Dominique 18 460 1.7.4 EMC 110,0 164,0 2271,5 1.7.5 IFR 37,5 Cost of IFR electronics estimated by Angelo 51,0 1239,0 1.7.6 Infrastructure 4 1.7.C 12 247 171,3 1.7.7 Systems Engineering AJR estimates 1.7.8 Hardware Trigger 97 Cost of Hardware Trigger electronics still based on BABAR's 532 369 1.7.9 ETD (without Trigger) 512 Cost of ETD electronics 990,0 D. Breton - SuperB Annecy Workshop - March 2010

D. Breton - SuperB Annecy Workshop - March 2010 What we expect from this workshop In the subdetector front-end session, the electronics contacts will summarize the design as described in the white paper and costing document This is the opportunity to verify all together the consistency of our proposal. This also is the last chance to modify the contents of the white paper and costing document This is also the role of the subdetector specific parallel sessions We would like feedback to the points raised just before. During the second session, all the elements of the architecture will be covered. All the progress and R&D will be described Next steps will be defined We hope to have a discussion about the level 1 trigger and its interaction with FCTS and FEE We now enter the pure TDR phase => we have to define our roadmap. => we have to define when real chip and board design have to start if ever some of these points were crucial for the final schedule D. Breton - SuperB Annecy Workshop - March 2010