Real time DSP Professors: Eng. Diego Barral Mr. Jerónimo Acencio Mr. Julian Bruno Eng. Mariano Llamedo Soria Eng. T. Ezequiel Blanca

Number representation and word-length effects. DSP fundamentals Number representation and word-length effects.

Recommended bibliography RG Lyons, Understanding Digital Signal Processing. Prentice Hall 1997. Ch9: Digital Data Formats and their effects. SW Smith, The Scientist and Engineer’s guide to DSP. California Tech. Pub. 1997. Ch4: DSP software. VK Madisetti, DB Williams. Digital Signal Processing Handbook. CRC Press. Ch3: Finite Wordlength Effects. SM Kuo, BH Lee. Real-Time Digital Signal Processing. John Wiley and Sons. Ch 3.4 to 3.6: DSP Fundamentals and Implementations Considerations. NOTE: Many images used in this presentation were extracted from the recommended bibliography.

Fixed point representation – Two’s complement system 011 3 010 2 001 1 000 111 -1 110 -2 101 -3 100 -4 Negation mechanism Step Result Original number 011=3 1 complement 100 Add 1 101 101=-3 Range -2N-1 to (2N-1-1) for N data bits Sign bit 011= 3 101=-3 DRdB = 20log(lv/sm) DRdB: Dynamic Range in dB lv: Largest possible value sv: Smaller possible value DRdB= 6.02dB . (N-1) One bit for sign, N-1 for number representation. Very popular system, widely used. Same logic for sum and subtraction.

Different interpretations Converting between Q formats Q15 means 15 bits for fractional part (aka 1.15) Q31 means 31 bits for fractional part (aka 1.31) Q12 means 12 bits for fraction 3 bits for integer Different interpretations bin Q2 Q1 dec 011 0.75 1.5 3 010 0.5 1 2 001 0.25 000 111 -0.25 -0.5 -1 110 -2 101 -0.75 -1.5 -3 100 -4 Converting between Q formats bin Q3 Q2 Q1 0111 0.875 1.75 3.5 0.111 01.11 011.1 Formats definition sign int . frac Total QX 1 M N 1+M+N Q15 15 16 Q31 31 32 Q12 3 12 /2N: moves dot N places left x2N: moves dot N places right Decimal equivalency for 1.X formats DRQ15 = 6.02*15 = 90.3 dB DRQ31 = 6.02*31 = 186.62 dB Fractional representation is equivalent to integer representation. Fractional dot could be placed arbitrarily anywhere. Most widely used formats are Q15 and Q31. Dynamic range is exactly the same than their integer counterparts “short” and “int” C language types. Range -1 to 1-(2-N) for N fractional bits

Dynamic range constraints Overflow a 2a … 7a 8a bin 0001 0010 0111 OV dec 0.125 0.25 0.875 Lost of precision a a2 … a6 a7 bin 0110 0100 0001 0000 dec 0.75 0.563 0.178 0.133 For non integer Q formats, multiplying large sequence of numbers cause loss of precision, but never overflow. For non integer Q formats, summing large sequence of numbers could cause overflow. Dynamic range is closely related with the two previous statements. The greater dynamic range, the smaller probability that overflow or loss of precision could happen. Remember that most DSP algorithms multiply and sum very often, so special care must be taken to prevent overflow or loss of precision.

Avoiding overflow Always use the maximum capability (guard bits) of the accumulators during internal calculations. Only round (or truncate) the final results to the final data size and format if possible. There is (almost) no lost of precision when handling internal calculations with guard bits.

Avoiding overflow System Scale Signal 0.9.β 0.8.β System Scale Signal Scaling down a signal is the most effective technique to prevent overflow. Scaling down always implies loss of precision. Both scaling down and guard bits techniques must be used in order to avoid overflow. Always is more convenient to scale down system’s coefficients instead of signals.

Avoiding overflow Effect of β in SNR Never overflows For example adopting β=0.5 implies a 6.02 dB decrease of SNR. This is equivalent that dividing by 2, rotating 1 time to the right, or losing 1 bit of resolution. More relaxed scaling Scaling down always reduces SNR. It is possible to use an absolute safe or a more relaxed criteria to choose β value. Many times it is preferable to use different Q fractional formats within an algorithm. As overflow is very probable to happen in fixed point processors, special effort should be taken when coding algorithms and debugging.

Minimizing overflow effects Without saturation arithmetic With saturation arithmetic Always use saturating arithmetic. In case overflow occurs, decrease the probability that an oscillation occurs.

Example of an overflow oscillation We have the following output For a system defined by: and an input: being the overflow rule: having a 4 bit word length, and no saturation arithmetic

Quantization word-length effects The codec and system’s coefficients are the main generators of quantization noise. Codec’s noise can be thought as a uniformly distributed PDF between –LSB/2 and LSB/2. The SNR of an ADC is proportional to the word-length and the loading factor.

Quantization word-length effects Complex conjugated two poles band pass And its difference equation When defining a system in term of its coefficients, the finite precision affect the behavior of the system itself. Though there is a grid of possible locations where system’s poles can be placed. This grid depends first of the word-length and second of the structure adopted to implement of the system.

Quantization word-length effects There are structures are less sensitive to coefficient quantization. There is a trade-off between efficiency and sensibility to coefficient quantization.

Floating point representation This form of representation overcomes limitations of precision and dynamic range of fixed point. This format segment data in sign, exponent and mantissa. Mantissa is represented as a fixed point number. Exponent is represented in binary offset format. The greater the be the larger the dynamic range. The greater the bm the larger the precision. There is a trade off between bm and be, and the best balance occur at be≈b/4 and bm≈3b/4.

Floating point representation (I) IEEE P754 is the most widely used floating point format. As the point is floating, a process called normalization is performed in order to use the full precision of bm bits, while the exponent is adjusted properly. Floating point arithmetic usually requires lot of logical comparisons and branching, so software emulated floating achieves low performance Floating point DSPs implements in hardware all arithmetic handling, so these DSPs outperforms their fixed point counterparts in ease of use and performance (of course being more expensive too).

Floating point representation (II) Single Precision (32 bits) Double Precision (64 bits) Sign Biased exponent Fraction Value Positive zero Negative zero 1 -0 Plus infinity 255(all 1s) ∞ Minus infinity -∞ NaN 0 or 1 ≠0 0 o 1 Positive normalized 0 < e < 255 f 2e-127 (1,f) 2e-1023 (1,f) Negative normalized -2e-127 (1,f) -2e-1023 (1,f) Positive denormalized f ≠ 0 2-126 (0,f) 2-1022 (0,f) Negative denormalized -2-126 (0,f) -2-1022 (0,f)

Normalized & Denormalized numbers (32-bit format ) Normalized numbers ( 1,f 2e-127) Denormalized numbers ( 0,f 2-126) Unused Gap = 1.4e-45 2-126 2-125 2-124 2-123 0 00000001 00000000000000000000000 Min. Positive Normalized 0 00000000 00000000000000000000001 Min. Positive Denormalized Gap = 2.8e-45

Multiply significands ¿X = 0? Z 0 RETURN ¿Y = 0? Add exponents Subtract bias Exponent overflow? Report overflow Report underflow Multiply significands Normalize Round No Yes

Division DIVIDE ¿X = 0? Z 0 RETURN ¿Y = 0? Z  Subtract exponents Add bias Exponent overflow? Exponent underflow? Divide significands Normalize Round Report overflow Report underflow No Yes