ATLAS Pixel Detector for HL-LHC P. Morettini ATLAS Pixel Detector for HL-LHC Paolo Morettini - PIXEL 2014 4/9/2014

High Luminosity LHC HL-LHC will start taking data in 2025, at a levelled luminosity of 5 x 1034 cm-2 s-1, with the aim of collecting 3000 fb-1. ATLAS will need a new tracker: Progressive radiation damage and intrinsic limitations in the FE chips will make the old detector inefficient More granularity and more bandwidth is needed to operate at HL-LHC, due to the large pileup. Paolo Morettini - PIXEL 2014 4/9/2014

ATLAS detector upgrade plan LS1 ↠ PHASE 0 ℒ = 1034cm-2s-1 <m>=24 100 fb-1 (2014-2017) LS2 ↠ PHASE 1 ℒ = 2x1034cm-2s-1 <m>=50 350 fb-1 (2019-2021) LS3 ↠ PHASE 2 ℒ =5x1034cm-2s-1<m>=140 3000 fb-1 (2023-2030) Installation of the 4th Pixel Detector Layer Pixel Detector improvements DBM beam monitor Silicon tracker cooling system replacement Muon EE chambers completion New Muon Small Wheel detector (keep same level of fakes with lumi increase) Upgrade of the central L1 trigger processor to allow topological L1 triggers LAr calorimeter electronics upgrade to increase L1 Calo granularity Hardware track trigger al L2 (FTK). Ussing associative memories. New “All Silicon” tracker New L0-L1 trigger schema Inclusion of track info in L1 trigger Upgrade of the calorimeter readout Upgrade of the muon spetrometer LoI submitted end 2012 Paolo Morettini - PIXEL 2014 4/9/2014

New “All Silicon” tracker (ITk) The layout proposed in the LoI provides 14 points/track to |n| < 2.7 Pixel: 4 layers + 5 disks, 25 x 150 (in) / 50 x 150 (out) mm2 Strips: 5 layers + 7 disks stereo Optional 5th Pixel Layer ~10 m2 of Pixels, ~200 m2 of Strips 650 M channels (Pixels), 75 M channels (Strips) 3200 10 Gb/s readout links. Same performance as the existing tracker up to m = 200 Paolo Morettini - PIXEL 2014 4/9/2014

Path to the TDR The design described in the LoI is what derives from the experience done with the existing detector and with the IBL. But, especially in the Pixel sector, new technologies are emerging, so we want, and in some case we must, do better. In this talk I will try to describe the options we are currently exploring in view of the preparation of a Pixel TDR in 2017. In the TDR we will show a complete design, with a very limited number of options, ready for the pre-production phase. ITk IDR Collaboration formed Strips TDR Pixel TDR Pre Production Production Installation 2014 2016 2017 2018-2019 2020-2022 2023-2024 Paolo Morettini - PIXEL 2014 4/9/2014

Things we can/must improve In the next two years, an intense R&D project will guide decisions on design and technologies, and hopefully will help us to improve on critical items: Readout speed, throughput Radiation hardness Pixel size, sensor thickness, dead zones Robustness, yield, quality control Cost Paolo Morettini - PIXEL 2014 4/9/2014

FE electronics At the time of the LoI, the trigger schema was a 500 kHz ROI based L0 (10% of the detector) , followed by a 200 kHz L1. In this context, the existing FE-I4 chip was a viable solution for the outer layers. We are now considering a full readout at 1 MHz, and this (together with the not so clear future of the IBM 130 nm process) suggests the adoption of the new 65 nm chip everywhere. 0.76 cm 2.02 cm FE-I3 50 x 400 mm2 250 nm (IBM) FE-I4 50 x 250 mm2 130 nm (IBM) FE-65 50 x 50 mm2 65 nm (TSMC) 1.11 cm 1.88 cm Paolo Morettini - PIXEL 2014 4/9/2014

New FE chip design (RD53) The new generation of Pixel FE chip is currently being designed in the framework of the RD53 collaboration. Cell size: 50x50 mm2 Compatible with 50x50 and 25x100 mm2 pixels (staggered contacts if needed) TSMC 65 nm technology Aim at 1000 e- threshold Constant power, can operate only a fraction of the channels Max Pixel capacitance 100 fF (to keep the amplifier design simple) Advanced clustering algorithms on-chip (to reduce bandwidth occupancy) 2 Gb/s serial output Full size prototype in 2 years Paolo Morettini - PIXEL 2014 4/9/2014

More challages… The idea of using the new readout chip everywhere brings a number of advantages. In particular, from the trigger point of view, the possibility of a full readout at L0 opens many opportunities. But there are side effects: A pixel size of 50x50 mm2 suggests a reduction of the sensor thickness (less than 150 mm) and requires low noise and low threshold operation. Signal transmission along the stave (electrically) and to the DAQ (optically) becomes even more challenging. This implies an increased R&D effort on data transmission lines and optical concentrators. Paolo Morettini - PIXEL 2014 4/9/2014

Chip output rate (Mb/s) Expected data rates From the LoI, extrapolated to 1 MHz trigger rate. Just a rough estimates. Currently recalculating with updated geometries and pixel sizes. The two innermost layers are obviously the critical point. Better compression mechanisms in the new chip can help. Layer Hits/cm2/BX Mhits/chip @ 1 MHz Chip output rate (Mb/s) 1 56 188 4000 2 20 67 1500 3 4 13 300 7 150 Paolo Morettini - PIXEL 2014 4/9/2014

Read-out chain Would like to try keeping with the approach of the present Pixel Detector, where we moved as much as possible critical items and possible bottlenecks outside the detector. But with up to 4 Gb/s per chip at 1 MHz L0, the problem can be in the electrical data transmission lines… Paolo Morettini - PIXEL 2014 4/9/2014

Signal transmission cables Several cables (twisted pairs, micro- coax) are under study to figure out maximum rates and lengths. Need ~1 m to get to the end of stave, ~3-4 m to get outside. Detailed simulations of the effect of extra material are needed. Paolo Morettini - PIXEL 2014 4/9/2014

Readout and trigger plans ATLAS trigger schema for HL-HLT: L0 : 1 MHz - 6 ms latency L1 : 400 KHz – 24 ms latency FE Data is transferred via fast optical links (GBT), then routed to destinations via a switched net (ETH, Infiniband…) Pixels : full readout at 1 MHz, but need to understand: Latency and resources needed in the track trigger to cope with L1 latency. Optical links: will a fast version of GBT be ready in time? Do we need aggregation in the inner layers? Paolo Morettini - PIXEL 2014 4/9/2014

Sensor development Many sensor types already in use in ATLAS: planar, 3D, diamonds. But improvements are needed for HL-LHC: Radiation hardness Smaller pixels Thinner sensors Small edges Uniform pixel efficiency Yield Cost Paolo Morettini - PIXEL 2014 4/9/2014

Radiation Fluences: 1 MeV neq.cm-2 7.7MGy , 1.4x1016n cm-2 0.9MGy , 1.7x1015n cm-2 0.9MGy , 1.8x1015n cm-2 Simulations with FLUKA to 3,000 fb-1 Paolo Morettini - PIXEL 2014 4/9/2014

Many detailed, very interesting, talks in the past days Sensors: overview Planar: a very well known technology, being adapted to Phase II requirements. 3D: used in the IBL. More expensive than planar, but easier to handle in high fluence environments, due to lower bias voltage. Need improvements in yield. Diamond: used in the DBM. Intrinsically rad-hard. Can operate without cooling. Expensive. CMOS “sensor replacement”: the outsider. Lot of potential, possible cost reduction, but first of all need to be demonstrated as a technology that can be used in a large scale detector. Many detailed, very interesting, talks in the past days Paolo Morettini - PIXEL 2014 4/9/2014

Planar sensor developments Bulk material (n-in-n and n-in-p, potentially cheaper) Thin sensors (150, 100 mm or less): less material, faster and more efficient charge collection, smaller cluster size) Smaller pixels (25 x 500 mm2 instead of 50 x 250 tested) Studies on slim/active edges. Full efficiency after irradiation demonstrated up to 2 1016 neq/cm2 at 1-1.5 kV. Paolo Morettini - PIXEL 2014 4/9/2014

Bias grid tuning Punch-trough structure for the biasing is known to produce inefficiencies that become relevant with small pixels after irradiation. Biasing with poly-silicon strips has been proved to significantly reduce these inefficiencies, especially if the routing is done avoiding the inter-implant zone. Poly-silicon resistors Efficiency profile (almost no asymmetry) Paolo Morettini - PIXEL 2014 4/9/2014

Quad modules Micron HPK CiS Various efforts to build and qualify “quad” modules, i.e. single sensor tiles bonded to 4 FE-I4 chips, to be used in outer layers. Different solutions are under test to cover the zone between the chips (long or ganged pixels). Stress compensation layers to reduce the bow during the bump-bonding process. Micron HPK CiS Paolo Morettini - PIXEL 2014 4/9/2014

25 x 100 ad 50 x 50 mm2 pads positioning 3D developments After the successful IBL installation, the 3D community is studying sensors optimized for HL-LHC. Small Pixels (50 x 50 preferred) Capacitance control, field simulation Thin sensors (different techniques: DWB, SOI, EPI) Slim or active edge 25 x 100 ad 50 x 50 mm2 pads positioning Thinning with DWB Paolo Morettini - PIXEL 2014 4/9/2014

HR/HV CMOS The dream would be to have a full monolithic pixel detector out of the foundry. Looks difficult at LHC rates. Diode (sensor) Analog (pre-amp) Digital (readout) Conductive coupling (bump) Diode Analog Digital Paolo Morettini - PIXEL 2014 4/9/2014

HR/HV CMOS The dream would be to have a full monolithic pixel detector out of the foundry. Looks difficult at LHC rates. But an intermediate step, possibly compatible with HL-LHC requirements and time scale, could be to include diode, pre- amp and discriminator into a single CMOS chip. The coupling of this “smart sensor” to the FE chip could be capacitive. Diode (sensor) Analog (pre-amp) Digital (readout) Conductive coupling (bump) Diode Analog Digital Capacitive coupling Potential savings in sensor and interconnection costs. Possibility to connect several small pixel to a single FE channel. Paolo Morettini - PIXEL 2014 4/9/2014

HR/HV CMOS We have a number of small prototypes of CMOS “smart sensors” that can be glued to a FE-I4 and operated in a test beam or irradiation setup. Encouraging preliminary results in terms of efficiency and radiation hardness, at least up to 1015 neq/cm2. A specific R&D is starting to evaluate this technology in time for the TDR. Full scale (FE-I4) prototype in 12-18 months. Points to clarify are: Charge collection efficiency Size of the active zone Radiation hardness Coupling to FE Sub-pixels Wire-bonds on back side vs TSV Large scale stability Cost. Paolo Morettini - PIXEL 2014 4/9/2014

Detector Layout The starting point is the LoI layout. A very traditional barrel/disk layout, based on our past experience, But the experts believe we can do better… Paolo Morettini - PIXEL 2014 4/9/2014

Pixel layouts under study Conical 5 Pix layars Rings Alpine Rings ext’d IBL ext’d Combinations are possible… Paolo Morettini - PIXEL 2014 4/9/2014

Rings Trying to facilitate service routing and to add flexibility, several options have been explored. Disks can be replaced with independent rings, that can be positioned at different z Paolo Morettini - PIXEL 2014 4/9/2014

Alpine In the Alpine layout, modules are attached to an inclined support. Again, much more flexibility in the positioning of the individual elements and the possibility to optimize the incidence angle, hence to reduce material. An alternative could be a conical section in the barrel… Paolo Morettini - PIXEL 2014 4/9/2014

Conical Bent staves can add flexibility in the barrel-to-endcap transition region: Can make the staves shorter, allowing a larger e coverage and a positioning at larger radius. Incident angle closer to normal at high η (less material, smaller clusters, less output bandwidth consumption). Paolo Morettini - PIXEL 2014 4/9/2014

Rings – High h The studies for the extensions of the tracking in the high h region (up to = 3-4), that could be beneficial for some physics channel (e.g. VBF), are producing even more layouts. More rings can be used to cover the high rapidity regions… Paolo Morettini - PIXEL 2014 4/9/2014

IBL extension – High h …or we could go for a very long barrel layer close to the beam pipe (like an extension of the IBL), and use the extremes of the cluster to compute Z0. Paolo Morettini - PIXEL 2014 4/9/2014

Lot of things! How to converge? How to converge to a consistent design in 2017? We need tools to compare different options: Clear definition of the requirements, in terms of mechanical, thermal, radiation characteristics and interfaces. More detailed studies on service routing. Performance benchmarks, possibly implemented at different simulation details (impossible to full-simulate every option). Evaluation of prototypes. Active participation to brainstorming and discussions Parametric cost matrix Paolo Morettini - PIXEL 2014 4/9/2014

Summary There are many interesting ideas and new developments on the table, and certainly this will give us the opportunity to build a better detector. However, we are far from having a coherent design. Need to make an effort to finalize our R&D program in the next two years, in order to be able to take decisions by the TDR. As usual, different development lines are not independent: the best detector design will emerge form the evaluation of the individual improvements in a common context. A lot of discussion and cooperation between the groups working on sensors, readout, integration, local support and simulation will be needed. Paolo Morettini - PIXEL 2014 4/9/2014

The ATLAS Pixel community The Pixel community is completing the effort of (re)- commissioning the old detector. A lot of experience has been accumulated, but obviously there is some conflict between the activities on the old and new detector. However, new groups are joining, bringing in new ideas and fresh views. The community keeps growing, and is ready for the HL-LHC challenge. Paolo Morettini - PIXEL 2014 4/9/2014