Alberto Valero 17 de Diciembre de 2007 OMB9U & ROD status Alberto Valero 17 de Diciembre de 2007

OMB 9U production All the components have been received except the Stratos optical connectors. We have to invite tenders for the optical connectors order because it costs more than 10.000€. The paper work needed will delay the reception until March. I contacted the Stratos Spanish representative and they are going to help us on this. We expect to receive the PCBs before the end of the year. I propose the assembly of one board using the optical connectors of the first the prototype to validate the PCB design.

OMB 9U status Developing the firmware needed in the OMB. New functionality almost ready: Sample generation for a given energy / phase ( per channel ). The pulse shape is stored hard-coded in the FPGA. Very useful for DSP code tests. The XTestROD OMB panel needs an update. We plan to update it before the end of year (Ximo). TDAQ panel – early 2008

ROD status From the last week Valencia TileCal DSP meeting we concluded (Arantxa – Belen - Ximo – Alberto): Add some new data quality checks at ROD level: DMU BCID, parity, bit 31 in header, DMU CRC & Global CRC. Ready M6 Channel-Killing (downloaded from database). Non instrumented Static problems OF no iterations ready to be tested in M6 (even if the phase is not well defined). Zero suppression needs new fragments. Has to be studied Muon Tag new fragment (Arantxa)

Event losses issue summary Running at high L1A rate we saw: Number events In DSP ≠ Number TTC events DSP Number events In DSP ≠ Number events In Staging FPGA Number events In Staging = Number TTC events DSP How the ROD works: Events are stored in a FIFO inside the Staging FPGA using a local oscillator of 40.00 MHz. The FIFO is read out using the TTC clock (40.08 MHz) which is lightly faster than the clock used to write. Hence, we have to wait before starting the read-out of the FIFO to avoid overwriting. In the previous version the read-out started when 64 words were received. Solution A new version of the Staging FPGA starts with 2 words and it is able to handle events separated by 4 BC. FE has to guarantee this separation between events. Tested in the lab with OMB

Event losses report

The problem Running at high L1A rate we saw: Number events In DSP ≠ Number TTC events DSP Number events In DSP ≠ Number events In Staging FPGA Number events In Staging = Number TTC events DSP It is, there are missing events in the DSP TM TTC Staging FPGA FIFO DSP Interface Board ROS Input FPGA OC

LV1A separation We must be able to handle LVL1 triggers separated by 5 Bunch Crossings (125ns). The FE – ROD link takes approximately 9us to transmit a 9 samples event. It implies a maximum event rate of 110 KHz. When the FE receive LVL1A when it is still sending previous events, the events are stored and send consecutively. Which is the minimum separation between two events ? 5 BC < 9us LVL1A > 5BC DATA 9us 9us

How the ROD works now Events are received from FE and stored in a FIFO inside the Staging FPGA using a local oscillator of 40.00 MHz. The FIFO is read out using the TTC clock (40.08 MHz) which is lightly faster than the clock used to write. Hence, we have to wait before starting the read-out of the FIFO, otherwise we would read the empty FIFO value. Up to now we started the read-out when we had received 64 words. Thus, when we write the last word of the event we should wait 64 clock periods before starting to write the next event to avoid overwriting. 40.00MHz 40.08MHz TM TTC Staging FPGA FIFO DSP Interface Board ROS Input FPGA OC

Solution The Staging FPGA code can be updated to start the FIFO read-out when we have received 2 words. 40.00 MHz  25 ns 40.08 MHz  24,95 ns We can transmit up to 500 words events before 2 clock periods “jitter” is reached. In this case, the separation between events should be at least 4 BC (100 ns). 40.00MHz 40.08MHz TM TTC Staging FPGA FIFO DSP Interface Board ROS Input FPGA OC

Tests at LAB TM Staging FPGA FIFO DSP OMB ROS Input FPGA OC With an homogenous LVL1A rate of up to 500 KHz. For the ROD point of view it is like LVL1A separated by 5BC since the Front-End buffer acts as derandomizer. Using the OMB as injector with a programmable separation between buffered events. The DSP has to stop the trigger generation when the TTC event input buffer has received 8 events ( size of the buffer is 16). TTC events are received in the DSP immediately whereas data events are received at the maximum event rate of 110 KHz ( 9 samples events). Then, the waiting time before discarding an event has to be increased in the DSP. 40.00MHz 40.08MHz TM TTC Staging FPGA FIFO DSP OMB ROS Input FPGA OC

Conclusions The problem has been reproduced in the lab, located and understood. We need an upgrade in the Staging FPGA code and in the DSP. It has been tested successfully in the lab with a separation between events of 100 ns (4 BC). We suppose a 4BC separation between events sent by IB. Separation between events Three consecutive events sent by the OMB to the ROD