ASKAP High Time Res Capabilities John Bunton High Time Res, Perth 15 April, 2009

Can only access high time res data at MRO control building Data Paths Can only access high time res data at MRO control building Data pipe from antennas already full ~40Gb/s to Geraldton 36beams, 16k channels 20Gb/s 4 dual pol 4-bit beams 20Gb/s MWA ????

DSP Processing card basics All processing at central site is on DSP boards Same DSP boards for Beamformers Correlator Tied array processor Four Processing FPGAs Input to FPGAs predetermined by design. Each Processing FPGA has single DRAM Two 10G outputs (total 8) Connection to control FPGA Control FPGA has two 1GE connections (includes control)

Beamformer Outputs Beamformer card process 19MHz of bandwidth for all elements and beams Split 5,5,5, and 4 MHz One of each 10G outputs per FPGA connects to correlator - One is available for high time res data But 576 outputs for ASKAP All FPGAs connect to control FPGA One 1GE output to control computer Some possibilities to use this data path for aggregation of low data rate outputs One 1GE output unused Example Auto correlations on 1GE

Transient Buffer Each FPGA has a DRAM Filterbank date 800MHz x 64 = 51Gb/s Assume 80% efficiency = 40Gb/s Filterbank date 5Mhz x36beam x2pol x 32bits/Hz x 2RW = 23Gb/s Excess bandwidth 17Gb/s Can write beam data to second buffer at 16 bits or less Fine filterbank needs ~250MB 750MB free per 5MHz BW 1 dual pol beam at 4bits = 100 seconds/GB

Transient Buffer Dump Can increase to 7.75GB = 775sec total @4bit = 10sec 36dual @4bit 18Tbytes total to process Real time dump of all beams requires 10GE ports. But normally dump one beam out of N at a time 0.3GHz x 2 pol x 8bits/Hz =2.4Gb/s Use 1GE port to dump at ~1/3 real time

Correlator Fast Dump Least data at low frequency resolution – min 1MHz Correlator has 128 DSP boards Simplest 2MHz per board 256MHz of bandwidth easiest to implement. Alternative 32 x18.5KHz channels per FPGA = 0.6MHz/FPGA = 2.4MHz/board Must code to average over frequency 0.6MHz at 0.97ms on board 10M correlation/sec/board 640Mb/s/board = single 1G link

Tied Array beams Beam data stored in DRAM on BF Fine filterbank process one dual pol beam at a time Data for one beam to correlator at one time Tied array beams formed in correlator – processing occurs at same time as correlations One beam at a time Currently one Tied array beam during correlation of one beam 36 beams gives 36 tied array beams With 18 or fewer beams process correlation in two stages Less than 1-1.2GHz large number of beams ~300 Requires extra correlator programming

Tied Array post processing All tied array data from 16 correlator shelves sent to single dedicated shelf for post processing Design not well thought out Intention to aggregate data and modify data rate For VLBI four tied array beams, BW 256MHz Sample rates 1 – 256MHz

MRO limitations Beamformer and correlator ~100kW Extra power dissipation ~$4/year/watt, $6/year/watt after cooling Extra 20kW = $120k per year OK Extra 60kW – not unless you pay the power bill Extra 20 to 60kW ???? Extra data to Geralton ~$80k for 10Gb/s

Thank you ICT Centre John Bunton Senior Principle Research Scientist ASKAP Project Engineer Phone: +61 2 9372 4420 Email: john.bunton@csiro.au Web: www.csiro.au/org/ICT.html Thank you Contact Us Phone: 1300 363 400 or +61 2 9545 2176 Email: Enquiries@csiro.au Web: www.csiro.au