Creation of a reference design in standard mode GBT-FPGA Tutorial Creation of a reference design in standard mode 27/06/2016 GBT-FPGA Tutorial – 27/06/2016

Outline What are the critical points of the latency-optimized mode? How to improve the design to use latency-optimized mode? How to constraint my design? How to debug the design? 27/06/2016 GBT-FPGA Tutorial – 27/06/2016

What are the critical points of the latency-optimized mode? Where are located the critical points? GBT BANK CFD 240MHz or 120MHz REFCLK 40MHz DPBC 240MHz or 120MHz TX_FRAMECLK Tx PLL Serial clock NLDC GBT_DATA GBT-Frame TX_USRCLK 84bit 120bit PISO TX Gearbox WB_EXTRADATA Scrambler Wide-Bus 32bit 120bit 120bit (Register) 20 or 40 bit TX_ISDATA_SEL Encoder Link n NLDC Transmitter NLDC GBT_DATA GBT-Frame Gearbox Barrel shifter Barrel Shifter 120bit SIPO CDR 84bit RX (Register) Pattern search WB_EXTRADATA Descrambler Wide-Bus 20 or 40 bit 32bit 120bit BitSlip control RX_ISDATA_FLAG Encoder Link n RX Frameclk gen. RXRECCLK Phase Algnr RX_FRAMECLK RX_USRCLK / 40MHz 240MHz or 120MHz Receiver RX_USRCLK CDR 240MHz or 120MHz CFD 27/06/2016 GBT-FPGA Tutorial – 27/06/2016

What are the critical points of the latency-optimized mode? How to configure the transceiver for the latency-optimized mode? NLDC: Non Latency Deterministic Components Clock domain crossing shall be made using register-based modules. CFD: Clock frequency division Rising edge of derived clock may lock onto any of the rising edge of the input clock. CDR: Clock and Data recovery Serial clock is divided by N to construct the usrclk. Dual data rate implies the recovered clock can latch on both rising and falling edge of the serial clock. State machine monitors the CDR to ensure a deterministic phase. IN Clk IN OutClk 27/06/2016 GBT-FPGA Tutorial – 27/06/2016

DEMO 27/06/2016 GBT-FPGA Tutorial – 27/06/2016

What are the critical points of the latency-optimized mode? How does the gearbox work in latency-optimized mode? Standard mode: based on RAM memory Latency-optimized mode: register-based Special case for TX Gearbox: external PLL 120bits @ 40MHz X Word 0 Gearbox 20bits @ 240MHz Init Invert input word and get [19:0] gearboxSyncReset = 0 rising_edge(tx_wordclk_240MHz) Invert input word and get [n+19:n] Invert input word and get [119:100] 27/06/2016 GBT-FPGA Tutorial – 27/06/2016

What are the critical points of the latency-optimized mode? Why does the TX gearbox is a special case? DPBC: Deterministic Phase Between Clocks External PLL 27/06/2016 GBT-FPGA Tutorial – 27/06/2016

What are the critical points of the latency-optimized mode? Why does the TX gearbox is a special case? Delay 1 /= Delay 2 Delay 1 = Delay 2 240MHz Delay 1 Transceiver TX_USRCLK 40MHz 240MHz TX_FRAMECLK Delay 2 X 120bit Gearbox 120bit (REGISTER) 20bit Meta-stability OK PhAligned 27/06/2016 GBT-FPGA Tutorial – 27/06/2016

What are the critical points of the latency-optimized mode? How the RX FrameClk (40MHz) is generated? Header sync 240 MHz RX_USRCLK RX_USRCLK X OK RX PhAligner Header sync (from frame aligner) RX_FRAMECLK 40MHz RX_FRAMECLK 27/06/2016 GBT-FPGA Tutorial – 27/06/2016

What are the critical points of the latency-optimized mode? What are the other solutions to generate the RX FrameClk (40MHz)? VHDL clock divider: Pros: no clocking resources Cons: worst jitter and require a special care for the constraints Clock enable: Pros: less clocking resources Cons: Duty cycle is not 50% 27/06/2016 GBT-FPGA Tutorial – 27/06/2016

DEMO 27/06/2016 GBT-FPGA Tutorial – 27/06/2016

How to constraint my design? 240MHz or 120MHz REFCLK 40MHz 240MHz or 120MHz TX_FRAMECLK < 25ns Tx PLL Serial clock GBT_DATA GBT-Frame TX_USRCLK 84bit 120bit PISO TX Gearbox WB_EXTRADATA Scrambler Wide-Bus 32bit 120bit 120bit (Register) 20 or 40 bit TX_ISDATA_SEL Encoder Link n Transmitter < 25ns GBT_DATA GBT-Frame Gearbox Barrel shifter Barrel Shifter 120bit SIPO CDR 84bit RX (Register) WB_EXTRADATA Descrambler Pattern search Wide-Bus 20 or 40 bit 32bit 120bit BitSlip control RX_ISDATA_FLAG Encoder Link n RX Frameclk gen. RXRECCLK Phase Algnr RX_FRAMECLK RX_USRCLK / 40MHz 240MHz or 120MHz Receiver RX_USRCLK 240MHz or 120MHz 27/06/2016 GBT-FPGA Tutorial – 27/06/2016

DEMO 27/06/2016 GBT-FPGA Tutorial – 27/06/2016