9/10/2018 JAZiO™ Incorporated JAZiO Presents to AMD

Agenda: Background JAZiO Solution Applications Design Considerations Sensing Timing Power Noise JAZiO Solution Applications Design Considerations

Sensing – Current Approaches Single ended Requires large signal swings Load dependent speed and power Not acceptable for high speeds Differential Very small signal swings Low power High speed But too many pins!!!

Sensing – Current Approaches Pseudo Differential At least three times the signal swing of full differential Higher power Lower speed Wouldn’t it be great to have the benefits of differential sensing without 2x the pins?

Timing Traditionally, digital switching requires: A fast transition Setup time Hold time (Perhaps) Return to Hi Z All referenced to a separate clock signal Very hard to scale these as data rates climb Wouldn’t it be great to avoid fast transitions and setup & hold times?

Power – Current Approaches Take your choice between larger signal levels for pseudo differential or 2x the pins for full differential Fast transitions  Low Z terminations, big drivers Return to Hi Z  Two transitions per data bit Critical skew to clock  PLL/DLL Wouldn’t it be great to have single pin per bit, low signal levels, slow transitions, no PLL/DLL and a single transition per data bit?

Noise – Current Approaches Noise on data signals may not track with VREF Large, fast transitions generate noise Large reflections due to fast transitions Wouldn’t it be great to have all common-mode signals and avoid large, fast transitions and have properly terminated lines?

JAZiO™ Solution

JAZiO Sensing Provide Voltage/Timing References, VTR and VTR both switching at the data rate Drive VTR and VTR coincident with data For each Data Input signal use two comparators: Compare Data Input to VTR (Comparator A) Compare Data Input to VTR (Comparator B)

JAZiO Sensing VTR Data is driven coincidentally with Voltage/Timing References VTR 1 2 3 4 5 6 7 8 8 different combinations of VTR and Data Input Data Input Bit Time Steering Logic Data Output VTR Input B A Dual Comparators are used In cases 1 and 6 Comparator A makes a differential comparison In cases 2 and 5 Comparator B makes a differential comparison In the other four cases Data Input does not change

Change /No Change Concept Comp A Change The time gap is used by the steering logic to pass the change or block the no-change from reaching the data output 1 No Change This band is based on process mismatch (device W, L, etc.), reflection or overshoot (discontinuity, termination, inductance, etc.). 3 Case 3: Comp A remains High (weakly) while the Data Output retains the previous data Change 1 Data In VTR Comp A Case 1: Comp A amplifies the change and the data passes through the Steering Logic

Alternating References VTR VREF Data Input Pseudo Differential Data Input JAZiO Instead of static VREF, JAZiO uses dynamic Voltage/Timing Reference (VTR) Larger differential signal when signal changes Reduces signal slew rate to achieve the same differential swing

when Data Input does not change Steering Logic The trick is to know how to select between Comparators A and B and what to do when Data Input does not change

Initialization Initialize data transmission with Data Input high and VTR going high to low (Bit Time 0) Initialize Data Output to High by the end of Bit Time 0 so it is stable high in Bit Time 1 (High) Bit Time 1 A VTR (High) Data Input VTR Steering Logic Data Output B Bit Time 0 During Bit Time 1, Comparator A should be enabled

Steering Logic Generate Steering Logic signals (SL and SL) B out in Data Input VTR XOR in Data Output XOR in out VTR SL VTR SL VTR Generate Steering Logic signals (SL and SL) Use them with Data Output from previous Bit Time to select between Comparators A and B

Data VTR Input SL Initialization or Data Receiver Enable Output SL XOR SL Initialization or Receiver Enable Data Output SL XOR Data Input VTR

JAZiO™ Receiver Operation Rail to Rail 1 SL XOR-B Data Output in out Input VTR B XOR-A Initialize Comparator Selected Differential ? CompB CompA A Yes Yes No A Yes Yes B No

JAZiO™ Receiver Operation Rail to Rail 1 SL XOR-B Data Output in out Input VTR B XOR-A Initialize Comparator Selected Differential ? CompB CompA Both Have Diff A Yes Yes No A Yes Yes B No Both Hi

The No-Change Case A B But! The handoff from Comparator A to B is smooth since both of them want to drive Data Output high After the handoff, Comparator B is ready to make the next differential comparison Comparator A is selected and as the differential on its inputs disappears the output remains high temporarily However, Comparator B is gaining a differential and its Output becomes a solid high VTR Data Input B A (High) Bit Time 3 Since Comparator A is selected its high value causes Data Output to remain high Data Output XOR-B in out XOR-A SL But eventually the XORs will switch And Comparator B will be selected

JAZiO Timing No clock signal is used, only VTR and VTR Data and timing are transmitted together Data and timing are “self-aligning” JAZiO has moved from voltage domain to the Time Domain

Voltage to Time Domain Transposition Above or Below Reference Peak to Peak Difference Change vs No Change Gap Vref Vol Voh pp D Change No Change Pseudo Differential Full Differential JAZiO JAZiO transposes the voltage domain to the time domain, since signal binary is defined in the time domain. JAZiO binary margin is more dependent on transition time rather than voltage swing.

18 JAZiO™ Receivers Data Output 0 Data Output 8 Data Output 9 XOR XOR SL SL XOR XOR XOR XOR XOR XOR Bits 10-16 Bits 1-7 SIGNALS FROM PADS VTR VTR Data Input 0 Data Input 8 Data Input 9 Data Input 17

I/O Interface Power Comparison 5000 I/O Power For 15pf & 30pf Load Cap. 4500 Current Single Ended Technologies The system can be optimized to achieve: Cost reduced package and lower system cost or Higher integration: more pins for more performance. 4000 3500 3000 Power (mW) 2500 2000 1500 1000 JAZiO™ (x16) (x16) 500 JAZiO-1000 JAZiO-2000 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 Giga Bytes/Second

"There are two kinds of designers, those that have signal integrity problems, and those that will". - Written on a whiteboard at Sun Microsystems The problems we commonly link in the general category of "signal integrity": signal quality, cross talk, switching noise and EMI, arise from the analog effects physical interconnects have on the pristine signals from the ICs. Though timing problems may be strongly influenced by the clock frequency, and the maximum cycle time available, it is predominantly the rise time that influences the magnitude of signal integrity problems in a system. - Signal Integrity Corner - Be Afraid, Be Very Afraid By Eric Bogatin, Bogatin Enterprises

I/O Interface Transition Time Comparison 10G Better JAZiO™ Reduced noise Improved margins Improved scalability 1G Bits per Second per Pin (b/S) RDRAM DDR DDR 100M SDRAM-100 SDRAM EDO 10M 6.4 3.2 1.6 0.8 0.4 0.2 Transition Time (nS)

I/O Interface Slew Rate Comparison 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Slew Rate (V/nS) Bits per Second per Pin (b/S) 10M 100M 1G 10G EDO SDRAM SDRAM-100 DDR RDRAM JAZiO™ Better Reduced edge current Reduced cross talk Higher reliability

Noise JAZiO works best with slow edges (use the entire Bit Time!) JAZiO works with small transition levels (differential sensing) Works with any Termination Scheme (Series, Parallel, Single, Dual, Source and even none in some applications) JAZiO is entirely common-mode

Power Supply Noise Issues Common Mode VTT Common Mode VTT JAZiO Signal VTR Common Mode Noise Sources VTT Common Mode VTT Signal Pseudo Differential VREF Noise Sources Noise Sources VSSQ noise between signal and VREF VTT noise and/or VTT mismatch on either end VREF impedance to Signal impedance mismatch

Environmental Noise Issues VTT VTT JAZiO Signal VTR VTT VTT Pseudo Differential Signal VREF Slower transition generates less noise in JAZiO Smaller transition generates less noise in JAZiO VTRs are isolated by VSS to eliminate noise variations Board dimensions have not shrunk as rapidly as on-chip dimensions

Less Noise; More Signal More Noise; Less Signal Environmental Noise Issues No Change (Low Victim) 0.5V JAZiO 2 On Hard 1 CASE 1 Narrower Band Less Noise; More Signal More Noise; Less Signal Wider Band Change (High to Low Victim) 1 VREF 0.8V Pseudo Differential 2 Slowly Turn On CASE 2 Noise (No Change) Noise (Change) No Noise (No Change) No Noise (Change)

JAZiO Delivers Sensing: Wouldn’t it be great to have the benefits of full differential sensing without 2x the pins? JAZiO provides differential sensing with single data pins Timing: Wouldn’t it be great to avoid fast transitions and setup & hold times? JAZiO allows slow transitions and self-aligned timing Power: Wouldn’t it be great to have single pin per bit, low signal levels, slow transitions, no PLL/DLL and a single transition per data bit? JAZiO has all of these Noise: Wouldn’t it be great to have all common-mode signals and avoid large, fast transitions and have properly terminated lines? JAZiO is completely common-mode with small, slow transitions and can support any termination scheme

Applications DRAM SRAM Front Side Bus On-chip Bus

DRAM Application Example JAZiO can be used between Controller and DRAM to achieve even greater than 2 GBit/pin/sec bandwidth JAZiO’s signaling technology allows bus expansion in both depth and width. No restriction on bus protocol or definition JAZiO is a low latency interface JAZiO makes implementation easier and takes the burden off of meeting set-up time, hold time, and rise/fall times. Requires no PLL or DLL Single cycle power-up initialization allows user to fully utilize standby/sleep mode Low power and wide operating frequency improves DRAM cost JAZiO’s small voltage swing and slow transition time allows multiple slots with terminations at both ends. Easily adaptable for large memory systems (like servers) Better performance and scalability CPU Controller L2 DRAM JAZiO

Address & Control Lines Address & Control Lines Lower Address & Control Lines Upper Address & Control Lines VTT 5 Bit Addr & Ctrl VTR0 VTR0 & VTR0 VTR0 CONTROLLER VTT VTT 5 Bit Addr & Ctrl VTT Clock Source Clock Data VTT VTR1 VTR1 & VTR1 VTR1 VTT Data VTT DRAM DRAM DRAM Upper Data Lines Lower Data Lines

Data Flow From Controller To DRAM Latch Delay Data Outs SL Deselection selection EVEN Cycle ODD Transmitter & Termination Controller Signals & VTRs DRAM VTT Receiver VTT CLK Signal delay can be used for pre-decoding of addresses or logical selection with control signals. VTR and VTR are used for latching signals

Read Cycle 8-Bit Burst TCAC TRCD TRCD ~20ns or 10 cycles 2-Pins CLK 2-Pins VTR0 TCAC VTR1 2-Pins RAS CS/RAS 1-Pin CS CS RAS TRCD CAS/WE 1-Pin CAS WE ADR 0:7/ ADR 8:15 Cols 8:15 8-Pins Rows 0:7 Rows 8:15 Cols 0:7 I/O 0:17 18 Pins TRCD ~20ns or 10 cycles TCAC ~20ns or 10 cycles

Write Cycle 8-Bit Burst TCWD TRCD TRCD ~20ns or 10 cycles 2-Pins CLK VTR0 2-Pins TCWD VTR1 2-Pins RAS CS/RAS 1-Pin CS CS RAS TRCD WE CAS/WE 1-Pin CAS ADR 0:7/ ADR 8:15 Cols 8:15 8-Pins Rows 0:7 Rows 8:15 Cols 0:7 I/O 0:17 18 Pins TRCD ~20ns or 10 cycles TCWD ~20ns or 10 cycles

Read, Read,Write, Read Burst 10 Cycles 10 Cycles 10 Cycles 10 Cycles CLK VTR0 VTR1 CS/RAS CAS/WE ADR 0:7/ ADR 8:15 I/O 0:17

Address & Control Lines Address & Control Lines Data 27:35 Data 18:26 DRAM DRAM Data VTT VTT VTR2 VTR2 & VTR2 VTR2 CONTROLLER VTT Data VTT Clock 5 Bit Addr & Ctrl VTT VTT VTR0 Clock Source VTR0 & VTR0 VTT VTR0 VTT VTT 5 Bit Addr & Ctrl Clock Data VTT VTR1 VTR1 & VTR1 VTR1 VTT Data VTT DRAM Lower Address & Control Lines Upper Address & Control Lines DRAM Data 9:17 Data 0:8

CPU to SRAM Application Example JAZiO can be used between CPU and SRAM (L2) to achieve huge bandwidth and low latency JAZiO bus can run at the same frequency as the internal CPU clock and include DDR (2 Gbit/sec per pin) Might use no terminations due to slow transitions and short lengths Control pin count on Back Side Bus Easily adaptable to support multiple cache sizes More external cache, less internal cache  smaller CPU die sizes No restriction and full differentiation on bus protocol and definition Better performance and scalability JAZiO CPU Controller L2 DRAM

9/10/2018 Front Side Bus JAZiO can be used in a proprietary bus between CPU and the Northbridge to achieve even greater than 16 GBytes/sec bandwidth. JAZiO bus can essentially run at the same frequency as the internal CPU clock with DDR. No restriction and full differentiation on bus protocol and definition. Lower cost in packaging and heat sink requirements due to reduced pins and power. Better performance and scalability. JAZiO CPU Northbridge L2 DRAM JAZiO Presents to AMD

Front Side Bus JAZiO can be used in a proprietary bus between CPU(s) and the Controller(s) to achieve many GBytes/sec bandwidth No restriction and full differentiation on bus protocol and definition MP snoopy bus or very high speed point-to-point For point-to-point, JAZiO bus can run at the same frequency as the internal CPU clock and include DDR (2 Gbit/sec per pin) Keep pin count growth and bus power under control Lower cost in packaging and heat sink requirements due to reduced pins and power Better performance and scalability L2 CPU JAZiO JAZiO Controller DRAM DRAM

Internal Application Example (SOC, Embedded, Etc.) JAZiO is well suited for large internal bus structures (SOC), which have greater than 2 pf/line loading. JAZiO uses ~0.3V swing with small transmitters and receivers to easily substitute traditional full swing buses. JAZiO also scales as the technology changes (process, voltage, etc.). JAZiO makes implementation easier and takes the burden off of meeting set-up time, hold time, and rise/fall times. JAZiO requires no PLL or DLL or repeater circuitry. JAZiO can support multiple frequencies on a given bus structure, it can be used synchronously or asynchronously, can support multiple supply voltages on the same bus, thus allowing the user flexibility in optimizing any implementation. JAZiO

What Does JAZiO™ Deliver? Sample layout and guidelines for receiver placement, small swing signal isolation and load matching. Simulation and netlist with critical conditions. Circuit options and testing strategy for signal skews from drivers, board and receiver mismatches. Consulting for design, debug and test chip evaluation (100 hours).