ABC130: DAQ Hardware Status Matt Warren et al. Valencia 3 Feb 2014

System Overview (Reminder from AUW) 2 Boards in the system have FPGAs: HSIO, Driver 2 modes of operation: Test Vector – PC loads data blocks, then “played” on L0/COM/Xoff etc. Results “recorded” on HSIO, then forwarded to PC for checking DAQ – normal data-taking – send COM, L0, L1, data decoded on HSIO Firmware functions distributed across boards: HSIO: Workhorse: memories, decoders and PC interface Driver: bi-dir buffers, clocks, “static” signals Data transferred to PC for verification - No buffers on Driver ABC clocks are generated on Driver from always-on BCO DRC too fast for inclusion with test vectors Single Chip Test Board HSIO Driver Board PC SCTDAQ FPGA Hybrid/ (Panel?) FPGA 3-Feb-2013 ABC130: DAQ Hardware Status

Reality: Single Chip and Driver Boards Designed, manufactured and tested by the Cambridge group See Bart’s talk from AUW: https://indico.cern.ch/getFile.py/access?contribId=14&sessionId=15&resId=2&materialId=slides&confId=233534 3-Feb-2013 ABC130: DAQ Hardware Status

Reality: On the bench HSIO 3-Feb-2013 ABC130: DAQ Hardware Status

Functions Detail Update Fast signals sent from HSIO to ABC via bi-dir buffers on Driver Driver mux’s bi-dir ABC sigs onto pairs of uni-dir HSIO links Slow (static) signals handled by direct connection of spare lines to HSIO register Limited to 16 bits TMU (Trouble Making Unit) control is ready when needed (128x32b possible) Communication with TMU is via L0COM line - Acts like another ABC has unique HCC and ABC address. Registers are in unused address space too Readback via a dedicated channel Driver handles bi-dir buffers 3 Modes of data to HSIO – Vector, Normal, Scan Driver Board HSIO BCO Single Chip Test Board BCO Clock Gen PC SCTDAQ Ethernet Network Interface 40MHz DRC 80/160MHz Control 3 L0COM,L1R3 Controls Sequencer DXOut 4 DATA, XOFF DXIn 4 Sink Decoder TMU Slow/static 16 Register e.g. Addr I2C 3-Feb-2013 ABC130: DAQ Hardware Status

Current Features Configurable clocks DRC at 80 or 160, and invertable Only 80MHz DRC working so far (HSIO issue) Data output can be tri-stated for testing Test vectors run at 160Mb Allows testing of all ABC130 functions at full rate Sequencer (vector playback): 8 bit 160Mb (uses 16b DDR @ 80Mb) 32kB (=100us) Small Sink (recording) Seq in reverse Fills then transfers multiple packets to PC I2C readback of Driver ADCs 2 modes of chip readout Normal: HSIO signals sent to L0,L1,COM etc pins Scan: signals send to boundary scan lines 3-Feb-2013 ABC130: DAQ Hardware Status

Future Features (the next 6 months) Get 160Mb ABC130-packet capture working on HSIO E.g. DRC=160MHz Larger Sink Increased sink to handle large readbacks Driver spys on ABC130 reg-writes to determine auto determine data direction ABC130 signals sampling at 320Mb: Optional 180 degree shift in sampling clock PER INPUT Neater data alignment Use TMU for control of all features More L0ID related firmware for L1 and R3 Auto generation of incrementing bursts Dual chip test board May need creative use of Driver resources (e.g. ABC addr pins) Vector based testing Wafer-probing 3-Feb-2013 ABC130: DAQ Hardware Status

Conclusion We have a working hardware system It will grow to match needs 3-Feb-2013 ABC130: DAQ Hardware Status