Hayri Uğur UYANIK Very Large Scale Integration II - VLSI II

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Presentation transcript:

Hayri Uğur UYANIK Very Large Scale Integration II - VLSI II Design for Testability Hayri Uğur UYANIK Devrim Yılmaz AKSIN ITU VLSI Laboratories Istanbul Technical University 03.06.2018

Outline Product Testing Production and Testing Outputs Production Yield Test Trade Offs Test Coverage Extremes Test Coverage Challenge Faults How to Detect Faults? Scan Flip Flop RTL Level Design Scan Chain How Scan Chain Works? Hard to Test Parts Cost of Test Time How to Test PCBs? References 03.06.2018

Product Testing Product testing is an expensive process, consuming: Time Resource Manpower Adding testability to design increases its Area Power Pin Count Design Time Production Time SO WHY DO WE NEED TESTING? 03.06.2018

Production and Testing Outputs Production and testing is never perfect 03.06.2018

Production Yield 03.06.2018

Test Trade Offs The only parameter that a test engineer can change is the Test Coverage Given infinite time and money, TC can be 100% Not practical TC is determined by the question: “How much does it cost to me if the design does not work?” The answer varies from one cent to million dollars 03.06.2018

Test Coverage Extremes 03.06.2018

Test Coverage Challenge Test should find the production defects on paths, devices, vias etc.. Today the largest chip has more than 2 billion devices Which is approximately the number of sand grains in one cubic meter Good luck with that! 03.06.2018

Test Coverage Challenge Alternatively we can only search for problematic cells, rather than defects Decreases the number of things to search Eases the search by assigning faults to each defect Can be done automatically using simple Boolean Logic 03.06.2018

Faults Stuck at zero Stuck at one 03.06.2018

Faults IDDQ Bridging 03.06.2018

Faults Transition 03.06.2018

How to Detect Faults? Simple: First apply an input to a cell, then measure the cell output Controllability: Can we change the state of a node? Observability: Can we observe the state of a node? If we assign pins to each node, we can both control and observe all of the chip Resulting with one million pins! 03.06.2018

Scan Flip Flop 03.06.2018

RTL Level Design 03.06.2018

Scan Chain 03.06.2018

Combinational Block Evaluates Scan Chain SE = 1 Combinational Block Evaluates SI Shifts to Q Result Arrives at D 03.06.2018

Scan Chain SE = 0 Result Shifts to Q 03.06.2018

Scan Chain SE = 1 Result Shifts to PO 03.06.2018

How Scan Chain Works? With the scan chain added, flip flops can be used as a shift register when SE = 1 This way all D inputs become observable, all Q outputs become controllable 03.06.2018

How Scan Chain Works? As a first step, the scan chain is tested by simply using it as a shift register Then in a shift register configuration (SE = 1), all Q outputs are loaded with a pattern Parallel Inputs (PI) are loaded (SE = 0) and all combinational logic evaluates using the pattern and PI. At the rising edge of clock input, (SE = 0) all D inputs take the result of the evaluation Then the scan chain returns to shift register configuration (SE = 1) and gives the results. Using this method, all combinational logic can be tested but is it worth it? 03.06.2018

Hard to Test Parts Hard to Observe Hard to Control 03.06.2018

Cost of Test Time Test patterns for scan chains are automatically generated by a tool called automatic test pattern generator (ATPG) For each fault type, ATPG can calculate the fault coverage Fault coverage approaches 100% if number of patterns goes to infinity 1 second of test time increases chip cost by 1 cent 03.06.2018

Cost of Test Time Suppose that, in a design, there are 100K FFs, clocked at 5 MHz. For the selected fault coverage, ATPG gives 15K patterns and the DFT section added 100 scan inputs. For each scan chain, there are 100K/100 = 1K FFs It takes 1K * 200ns * 15K = 3 seconds to test Increases chip cost by 3 cents 3 cents is more expensive than you think! The tester needs to process 100K * 15K * 2 = 3Gb input / output data in 3 seconds 03.06.2018

How to Test PCBs? Boundary Scan Insertion 03.06.2018

How to Test PCBs? 03.06.2018

How to Test PCBs? Boundary Scan Cell 03.06.2018

How to Test PCBs? Boundary Scan Cell Transparent Mode: Capture Mode: SHIFT = 0, MODE = 0, PI goes to PO Capture Mode: SHIFT = 0, MODE = 0, CLK ↑ Update Mode: SHIFT = 1, MODE = 1, CLK ↑, UPDATE ↑ Scan Mode: SHIFT = 1, MODE = 0, CLK ↑ 03.06.2018

How to Test PCBs? Boundary Scan Chain in a chip can be controlled by a state machine called Test Access Port (TAP) Controller With a Boundary Scan added PCB, using four inputs, one can.. detect PCB defects control and observe chip I/Os test the chip using internal scan chain program the chip send commands watch outputs 03.06.2018

References Inan Erdem, Personal Talk, March 2010 http://www.asset-intertech.com/pdfs/Boundary-Scan_Tutorial_2007.pdf 03.06.2018