PCIe control interface for user logic.

PCIe CONNECTIONs Avalon MM is an interface that provides read/write address based access. Possible usage: Single Master to control all the Slaves (selection will be done using add. range on the Slave side) Different Masters connected to different Slave, point to point connection, as showed in the picture (selection will be done in the PCIe wrapper)

AVALON master signal interface AVALON MM implements ADD + DATA transfers in 2 directions. The Master can write data to the Slave. The Master can read data from the Slave. Burst operation is supported by the protocol.

Signal configurations There are mainly 3 type of transfer to be handled by the user logic: Pulse signals: active for one or more than one clock cycle Enable/disable signals: active until the command disables them Register configuration. Example of pulse signals : reset Example of toggle signals : enable Example of register : configure a 32 bit register in the user logic, set configuration values.

WAVE form (burstcount = 1) Example Master Slave transfer: Data is valid only when write is ‘1’ The transaction is frozen if the slave rises the waitrequest signal

Example : RESET generation rst <= '1' when (avm_write = '1' and avm_address = x"00000524“ and avm_writedata(0) = ‘1’) else '0'; --! component to extend the reset signal for CC clock cycle cmp_gen_reset : entity work.gen_reset generic map (CC => 10, POL=>1) port map ( clk => clock, i => rst, o => reset );

GEN RESET component entity gen_reset is generic (CC : integer := 10, POL : integer := 1); port ( clk : in std_logic; i : in std_logic; o : out std_logic ); end gen_reset; architecture rtl of gen_reset is signal cnt : integer range 50 to 0; signal s : std_logic; begin o <= s when (POL = 1) else not(s); s <= '0' when (cnt = 0) else '1'; p_cnt : process(clk) if rising_edge(clk) then if i = '1' then cnt <= CC; else if cnt > 0 then cnt <= cnt - 1; end if; end process; end rtl;

ENABLE signal ena <= '1' when (avm_write = '1' and avm_address = x"00000524“ and avm_writedata(1) = ‘1’) else '0'; cmp_toggle_signal : entity work.toggle_signal port map ( clk => clock, i => ena, o => cluste_finder_enable );

TOGGLE signal entity toggle_signal is port ( clk : in std_logic; rst : in std_logic; i : in std_logic; o : out std_logic ); end toggle_signal; architecture rtl of toggle_signal is signal s : std_logic; begin o <= s; p_cnt : process(clk) if rising_edge(clk) then if rst = '1' then s <= '0'; else if i = '1' then --! This is a pulse of 1 CC s <= not(s); end if end if; end process;

BURST tranfer The AVALON MM interface allows the transfer of several words. The size of the BURST is 1< BURST <2x-1 A burst executes multiple transfers as a unit, rather than treating every words independently. Slave can delay a transfer by asserting waitrequest signal, forcing the master to old the value of writedata, write, burstcount and byteenables signals 1 2 3 4 5 6 7

Timing Avalon interfaces must be edge sensitive only to clock and reset. The Avalon interface should be able to operate properly, running @ 250 MHz (PCIe interface clock). The user logic doesn’t have to run at such speed, however to easy the communication and the handling of the signals the 2 AVALON interfaces should run at the same clock speed. The Clock Domain Crossing will happen after/before the interface CLK2 CLK1 CDC AVALON SLAVE AVALON MASTER