SLS-CS_13-02 High Data Rate (Gbps +) Coding Architecture Fall Technical Meeting, Bordeaux (BOD) 4/15-18/2013 SLS-CS_13-02 High Data Rate (Gbps +) Coding Architecture Part 2 (part 1 was presented at Fall 2012 meeting) V. Sank, H. Garon - NASA/GSFC/MEI W. Fong, W. Horne – NASA/GSFC 1

High Data Rate (Gbps) Coding Architecture Purpose To avoid having a transmitter encoder built in a way that is incompatible with the ground receiver decoder, a standard or recommendation should exist. Introduction Inherent to any system is the problem of component rate limits. In addition to the encoder and decoder, the circuits that compose the I and Q or higher order modulation channels, hit a rate limit. If there was only one way to architect the system, there would be little concern. The problem is that there are several ways to build the system and the transmitter must have the same structure as the receiver. As we push to very high rate Gbps links, we believe that CCSDS should set standards on how encoders and decoders should be multiplexed. Vendors are ahead of CCSDS and several have already chosen an architecture. Our intent here, at a minimum, is to make the community aware that a laissez-faire approach towards standards is a poor choice. Since there are multiple structures possible, every user must clearly specify their intended structure and must insure that the encoder and decoder are compatible.

High Data Rate (Gbps) Coding Architecture Background In days past, in a case with a convolutional code, and rate limited decoders, several decoders were required. Not realizing that there was more than one way to architect the system, the vendor chose what was thought to be the only or obvious structure, and built the spacecraft. It was not until after CDR and after the spacecraft was built, that we asked the vendor how he knew what the ground station design was. It turned out that the spacecraft was built incorrectly and the transmitter encoder needed to be disassembled and redesigned. The spacecraft vendors test equipment also needed to be redesigned. Scope the intend of this presentation is to have CCSDS consider a standard This presentation is not intended to be a design document or specification. The following diagrams do not consider the latencies, memory buffers and frame synchronization that will be required in a formal specification or real system.

High Data Rate (Gbps) Coding Architecture R = data rate (from C&DH) (bits/sec) R = coded data rate (code symbol rate) = Rs (code symbols/sec) N = number of encoders k = codeword message size (bits) n = codeword size including parity (bits) m = modulation order (ie. m=3 => 8PSK) s = size of ASM (in same units as k and n (bits, nibbles, bytes)) mPSK m order Modulator R Mapper Code symbols to Modulation Symbols Data Source R R/m R Block Code Encoder Modulation symbol rate = R/m R = (n+s)/k R Transmitter Diagrams are shown from the point of view of the transmitter. The structure of the decoder must complement the transmitter, except as noted.

Recommended Architecture Block Encoder Input, Block output (codeword in – codeword out) Block Code Encoder b1, b2, b3, ... R R/N c1, c2, c3, ... mPSK R = (n+s)/k R Block Code Encoder b1, b2, b3, ... c1, c2, c3, ... mth order Modulator R/N Mapper Code symbols to Modulation Symbols Data Source R R R b1, b2, b3, ... Block Code Encoder R R/N c1, c2, c3, ... Modulation symbol rate = R/m b1, b2, b3, ... Block Code Encoder R R/N c1, c2, c3, ... An encoder is loaded with the full message size, k, before data starts flowing into the next encoder. (receivers from two vendors are configured this way. ) Data on the physical channel appears the same as it would if there was a single encoder that runs at the full rate. This architecture has the advantage that the number of encoders and decoders need not be the same. 5

Recommended Architecture With OQPSK Modulation Block Encoder Input, Block output Data from a single encoder is staggered onto the I and Q channels Block Code Encoder b1, b2, b3, ... R R/N c1, c2, c3, ... OQPSK Block Code Encoder b1, b2, b3, ... c1, c2, c3, ... c1, c3, c5, ... Modulator R R R/N Data Source R R R/2 b1, b2, b3, ... Block Code Encoder Mapper R/2 R R/N c1, c2, c3, ... c2, c4, c6, ... b1, b2, b3, ... Block Code Encoder For 7/8 LDPC code there will be 0 Modulation symbols that cross a boundary. R R/N c1, c2, c3, ... Data on Physical channel appears the same as if there was a single encoder that runs at full rate, R. This architecture has the advantage that the number of encoders and decoders need not be the same. Four encoders shown but the number depends on the rate capability of the encoders and decoders. 6

Recommended Architecture With 8PSK Modulation Block Encoder Input, Block output Data from a single encoder forms a modulation symbol One encoder is loaded before switching to the next. Block Code Encoder b1, b2, b3, ... R R/N Except at Block boundary c1, c2, c3, ... 8 PSK R/3 Block Code Encoder b1, b2, b3, ... c1, c2, c3, ... c1, c4, c7, ... Modulator Data Source R R R/N R R R/3 b1, b2, b3, ... Block Code Encoder Mapper c2, c5, c8, ... R/3 R R/N c1, c2, c3, ... c3, c6, c9, ... Currently, Data Rates Greater than 1 Gbps Require 8PSK Note that this Architecture does not use a separate encoder for each of the 3 channels. For every 3 codewords there will be 2 Modulation symbols that cross a boundary. Data on Physical channel appears the same as if there was a single encoder that runs at full rate, R. This architecture has the advantage that the number of encoders and decoders need not be the same. Three encoders shown but the number depends on the rate capability of the encoders and decoders. 7

NOT Recommended Architecture With OQPSK Modulation Staggered Encoder Input, and Output Possible OQPSK configuration Similar to RS code block NOT Recommended Block Code Encoder b1, b5, b9, ... R/N c1, c5, c9, ... OQPSK Block Code Encoder b2, b6, b10, ... c2, c6, c10, ... c1, c3, c5, ... Modulator Data Source R R/N R/N R R/2 b3, b7, b11, ... Block Code Encoder Mapper R/2 R/N c3, c7, c11, ... c2, c4, c6, ... b4, b8, b12, ... Block Code Encoder R/N c4, c8, c12, ... This configuration has the same advantage as the RS code block, burst protection. M  average number of codeword errors that can be corrected over all codewords. On average, this configuration will correct a burst of N*M bits because consecutive bits on the physical channel are from different encoders. An implementation that is expecting a high burst noise background may prefer such a custom design where bits are staggered into and out of the encoder. (more detail on next slide) 8

NOT Recommended Architecture RS Type Frame applied to 7/8 LDPC b1 b2 b3 b4 b5 b6 b7 b8 n = 8160 28545 28546 28547 28548 32637 32638 32639 32640 32 bit CSM k = 7136 n-k = 1024 I = 4 Bits are loaded horizontally and transmitted in the same order. (Staggered IN, Staggered OUT) Four separate codewords shown. Codeword 1 contains bits b1, b5, … , 32637. If a burs t of noise corrupts bits 5,6,7,8 on the physical link, the decoder will see only one error in each of the 4 codewords. This configuration is used for Reed-Solomon coding where the code word is only2040 bits long. This configuration is not generally required for the 7/8 LDPC code due to its larger size and better burst error correcting ability. When this configuration is used, the receiver must be set up with the same number of decoders as used in the encoder. CCSDS may decide to choose this as the recommended Gbps coding structure, rather than the structure shown on slides 5, 6, and 7. If the encoder and decoder can handle the full data rate, I can be set to 1 and the result will be the same structure on the physical channel as the recommended architecture. . 9

Concepts that apply to RF also apply to Optical communications. High Data Rate (Gbps) Coding Architecture Conclusion: To avoid confusion, examples of architectures which are not recommended are just as important as those which we do recommend. Concepts that apply to RF also apply to Optical communications. However, for optical communications, a different code block structure (similar to the RS structure) may be desired. CCSDS should recommend standard before we have vendors building Gbps systems that are incompatible with each other. 10

High Data Rate (Gbps) Coding Architecture Back Up 11

Encoder, Simple Cases Recommended Architecture Recommended BPSK Data Source R Modulator R Block Code Encoder Recommended Architecture Mapper Single encoder Limited rate Simple OQPSK C1, C3, C5, ... Modulator Data Source R R R/2 Recommended Architecture Block Code Encoder Mapper R/2 Single encoder Limited rate C2, C4, C6, ... Simple Same decoder configuration as above Staggered Encoder Input Independent Encoders on the I and Q channel Block Code Encoder OQPSK b1, b3, b5, ... c1, c2, c3, ... Modulator Data Source R R/2 R/2 Not Recommended R/2 Block Code Encoder R/2 b2, b4, b6, ... c1, c2, c3, ... Not so simple Requires unique decoder configuration When more than 1 encoder, input is shown as either b1 b2 b3 which means that a constant stream of bits are input, or b1 b3 b5 and b2 b4 b6 which means that the bits are staggered from one encoder to the other.

Quad Encoder, 16PSK possible configuration Block Encoder Input, Block output Possible 16PSK configuration RECOMMENDED Block Code Encoder b1, b2, b3, ... R/N c1, c2, c3, ... 16PSK R/4 Block Code Encoder b1, b2, b3, ... c1, c2, c3, ... s1, s2, s3, ... Data Source R R/N R/N R s1, s2, s3, ... 4th order Modulator b1, b2, b3, ... Block Code Encoder Mapper s1, s2, s3, ... R/N c1, c2, c3, ... s1, s2, s3, ... b1, b2, b3, ... Block Code Encoder Rchannel symbol = R/4 s1, s2, s3, … are modulation symbols R/N c1, c2, c3, ... 8192/4 = 2048 This architecture has the advantage that the number of encoders and decoders need not be the same. On average, this configuration will correct a burst of N bits, not N channel symbols A cover code can be used to synchronize the decoders and resolve ambiguity. 13