CCS Hardware Test and Commissioning Plan ECAL Off-Detector Electronics Workshop 7-8 April. 2005 Kostas Kloukinas CERN

Overview CCS Development Status Production Plan CCS during Integration and Commissioning 7/4/2005 Kloukinas Kostas

The FEC-CCS System FECtracker = CCSecal* Design satisfy the requirements from: Tracker ECAL Preshower Pixel RPC Three components: mFEC: small mezzanine card suitable for VME and PCI utilization. PCI-carrier: motherboard for one mFEC FEC-CCS: VME motherboard for 8 mFECs. FECtracker = CCSecal* 7/4/2005 Kloukinas Kostas

mFEC & PCI carrier mFEC on a PCI carrier board to facilitate development work to be used in the lab and test beams. 7/4/2005 Kloukinas Kostas

FEC-CCS V2 (Prototype) mFECs VME backplane ECAL backplane TTC input VME Interface FPGA mFECs VME backplane ECAL backplane TTC input Trigger FPGA 7/4/2005 Kloukinas Kostas

FEC-CCS V3 (Final) V2 to V3 modifications: One board assembled. Splitting of 1-wire bus for temperature sensors and serial ID chip. Reassignment of JTAG backplane signals. QPLL & TTCrx control lines. Routing of spare FPGA lines at the P2 connector. One board assembled. Tested O.K. 7/4/2005 Kloukinas Kostas

Prototype Test Status VME to Local Bus interface is O.K.. All 8 mFECs can be and accessed from the VME bus. Conforms to the VME 64x “plug & play” standard. VME Interrupter is tested. Various Functions Electronic Serial Number tagging using a serial ID chip. Airflow temperature monitoring of the OPTOBAHNs on mFECs Fast Timing path is tested. TTCrx – Trigger FPGA – mFECs – control rings. Send trigger commands to FE and DCC. Power consumption (measured) Card fully equipped with 8 mFECs 7A @ 3.3V, 1A @ 5.0V => ~30W dissipated Pending Issues: TTS signal functionality. DCC-CCS-TCCs integration tests. VME bus JTAG basckplane controller access. 7/4/2005 Kloukinas Kostas

Pre-Production Status FEC-CCS: Version 1: First prototype. 2 units have been fabricated. Were used in the TRACKER test beam and in the ECAL test-beam setups (summer 2004). Version 2: Second prototype. 8 units have been fabricated. All units are tested and fully equipped with mFECs. They are available for distribution. Version 3: Final version. Pre-production of 10 boards is in progress. 1 unit delivered (11/3) and currently being tested 9 more will be delivered around early April. 7/4/2005 Kloukinas Kostas

FEC-CCS Test Bench XDAQ (HAL) framework Full plug&play support Software development by: E. Vlassov F. Drouhin CERN scientific Linux >_ 7/4/2005 Kloukinas Kostas

Component Traceability Managing the distribution of FEC-CCS boards. FEC-CCS Project Website: proj-fec-ccs.web.cern.ch/proj-FEC-CCS 7/4/2005 Kloukinas Kostas

Final Production Tracker: 352 control rings => 44 FEC-CCS boards ECAL: 368 control rings => 46 FEC-CCS boards Preshower: 48 control rings => 20 FEC-CCS boards Pixels: 120 control rings => 16 FEC-CCS boards RPCs: 25 control rings => 4 FEC-CCS boards ----------------------- 130 FEC-CCS boards 116 FEC-CCS boards => 930 mFECs 50 PCI FEC boards => 50 mFECs ---------------- 980 mFECs Spares should be added…. 7/4/2005 Kloukinas Kostas

Production Schedule Production of 900 mFECs is in progress. Production of 140 FEC-CCS boards to start soon. All components have been procured PCB manufacturing and assembly companies found. Production Testing Will be done at CERN Test bench and test procedures are currently under development. 7/4/2005 Kloukinas Kostas

Integration & Commissioning FEC-CCS board should facilitate: Front-End system testing & debugging. Possibility to run DCC-CCS-TCC(s) standalone. Enable data taking when LTC-TTCci system is unavailable. 7/4/2005 Kloukinas Kostas

Final System TTC/TTS signal paths TTCmi Global Trigger Controller Controller FMM TTC Local Triggers TTS TTC ci TTC ci TTC ci TTC ci TTC ex TTC ci TTC ci TTC ex TTC ci TTC ci TTC ex Controller LTC TTS CCS CCS CCS CCS DCC TCC DCC TCC DCC TCC DCC TCC Controller TTC 7/4/2005 Kloukinas Kostas

FEC-CCS during Integration When final System is not yet available / operational Requirements: Enable Slow Control for the FE electronics. Generation of Local Trigger Commands and their distribution to the FE and to the OD electronics. Off-Detector electronics (DCC, TCCs) synchronization at the level of one supermodule. Implementation: Hardware Interface with external signals to synchronize internal operations. Firmware Trigger FPGA functionality to allow the generation and distribution of the Local Trigger Commands. Software To support these functionalities. 7/4/2005 Kloukinas Kostas

FEC-CCS Block Diagram Support for 1~8 control rings per board. VME 9U board. VME64x compatible. Control information passes through the VME bus. Fast Timing Signals passes through the TTC link. mFEC Local Bus VME interface FPGA VME bus mFEC mFEC Fast Timing signals JTAG mFEC mFEC mFEC Trigger FPGA External I/O mFEC mFEC QPLL TTCrx TTC link ECAL TTC/TTS bus 7/4/2005 Kloukinas Kostas

FEC-CCS Piggy Back Board ECAL Test Beam Summer 2004 Trigger FPGA logic. Prepared by Mark Dejardin 7/4/2005 Kloukinas Kostas

FEC-CCS Multi I/O board As a replacement of the Piggy Back I/O board. Propose to build a 3U Rear VME Backplane Transition Board Connects on spare Trigger FPGA lines. Only FEC-CCS V3 supports this card. LVTTL to NIM NIM to LVTTL VME RJ2 connector NIM I/O 4 IN 4 OUT 1 clock in 1 clock out (+ 4 IN/OUT spares) LVTTL I/O 7/4/2005 Kloukinas Kostas

Trigger FPGA firmware design CCS Local Bus Trigger FPGA Piggy Back Board Trigger Command Manager Local Bus interface & Control Registers 4 NIM to TTL TTL to NIM translators IN Clk40_L1 to mFECs 4 OUT CCS Clock Clk40_L1 TTCrx L1ACCEPT L1 Token Ring Clock Encoder BRCST<7:2> 110 101 TTCRX_RDY 111 Clk40 Clk80 QPLL 40MHz TTC in L1 TTC Encoder 80MHz B<7:0> 160MHz Clk40 Clk40 Clk160 TTC signal to DCC/TCCs 7/4/2005 Kloukinas Kostas

Trigger Command Manager (1/4) FEC-CCS modes of operation REMOTE: Trigger Commands as received from the TTCrx chip are being distributed to Token Rings and the ECAL backplane. Used for Normal Data Taking operation. LOCAL: Allow the generation of Local Trigger commands. Used for system debugging. Mode Selection Auto Remote/Local selection is automating depending on the status of the TTCRX_RDY signal. Forced LOCAL User selection 7/4/2005 Kloukinas Kostas

Trigger Command Manager (2/4) Mapping of TTC B channel commands to Token Ring Trigger Commands Trigger Command Assignments on the Token Rings are not common between subsystems. The FE ASICs decode these commands in a fixed manner. Mapping of TTC B channel commands to Token Ring Trigger Commands can be done by a LUT in the Trigger FPGA. 7/4/2005 Kloukinas Kostas

Trigger Command Manager (3/4) Generation of Local Trigger commands Local L1 Trigger Command. LOC_L1 command channel External signals Internal signals 7/4/2005 Kloukinas Kostas

Trigger Command Manager (4/4) 7/4/2005 Kloukinas Kostas

Wrap Up Flexible and configurable logic allows for: Generic design Single shot commands. Single shot Bursts of commands. Sequence of multiple commands. Periodic Sequence of multiple commands. Synchronization with external signals. Generic design The Integration Physicist/Engineers can modify the Trigger Generation logic as required for their setup. Other sub systems could possibly utilize these functionalities Easy firmware maintenance. Unique version for all subsystems. Comments & Discussion….. 7/4/2005 Kloukinas Kostas

Backup Slides 7/4/2005 Kloukinas Kostas

Piggy-Back PCB R. Benetta, M. Dejardin 7/4/2005 Kloukinas Kostas

FEC-CCS Piggy Back I/O board Prepared for the ECAL Test Beam in Summer 2004. by Mark Dejardin 7/4/2005 Kloukinas Kostas

Trigger FPGA Registers Available only for the ECAL Test Beam summer 2004 7/4/2005 Kloukinas Kostas

Trigger FPGA design Trigger FPGA Piggy Back Board CCS Local Bus BOB ECAL Local Trigger Management Logic Local Bus interface & Control Registers NIM to TTL TTL to NIM translators Clk40_L1 to mFECs EOB Laser In TDC Start TDC Stop Clk40 Clk40_L1 Laser Out Trigger Insertion Logic Loc L1 CCS Clock Clk40 Clk40 Clk40_L1 TTCrx QPLL 40MHz Clock Management Logic 160MHz TTC signal to DCC 7/4/2005 Kloukinas Kostas

Overview of CCS Board 7/4/2005 Kloukinas Kostas

FEC-CCS Production Testing Production Testing will be done at CERN Separate Test Benches: For the mFECs will be PC based. Using PCI carrier boards. For the FEC-CCS boards will be VME based. Hardware needed: PCI bus, preferably allowing hot plug-in. TTC/TTS backplane driver board. TTCvi or TTCci . Software needed PC software for mFEC testing Linux software for FEC-CCS testing. 7/4/2005 Kloukinas Kostas