Seoul National University Introduction

Why do you want to study Computer Architecture? Seoul National University Why do you want to study Computer Architecture? Because….You won’t graduate if you don’t take this course. Because….You want to design the next great instruction set. Instruction set architecture has largely converged, especially in the desktop/server/laptop space. Dictated by powerful market forces (Intel/ARM). Because….You want to become a computer architect and design the next great computer systems. Because….The design, analysis, implementation concepts that you will learn are vital to all aspects of computer science and engineering – operating systems, computer networks, compiler, programming languages Because….The course will equip you with an intellectual toolbox for dealing with a host of systems design challenges And much more !!! From Prof. Fernando C. Colon Osorio’s lecture notes

Course Goals To understand Interfaces Seoul National University Course Goals To understand Interfaces Instruction Set Architecture (ISA) – The Hardware/Software Interface Engineering methodology / Correctness criteria / Evaluation methods / Technology trends involved in Processor Cache memory Virtual memory I/O system

Textbooks Randal E. Bryant and David R. O’Hallaron, Seoul National University Seoul National University Textbooks Randal E. Bryant and David R. O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition (CS:APP3e), Pearson, 2016 http://csapp.cs.cmu.edu Brian Kernighan and Dennis Ritchie, The C Programming Language, Second Edition, Prentice Hall, 1988 Still the best book about C, from the originators

Source : http://www.webster.com Seoul National University Interface Source : http://www.webster.com

Abstract Data Type (ADT) as an Example of Interface Seoul National University Abstract Data Type (ADT) as an Example of Interface Abstract data type : A set of data values (state) and associated operations that are precisely specified independent of any particular implementation ADT Example : stack push pop (top) Create_stack Destroy_stack ·· (bottom) stack S is_empty

Abstract Data Type (ADT) as an Example of Interface Seoul National University Abstract Data Type (ADT) as an Example of Interface Operations viewed as state transformation 4 Push (s, 4) 5 5 1 1 2 2 S S` (Before) stack (After) stack

Abstraction Before After Seoul National University Abstraction Before After Jeff Kramer, “Is Abstraction the Key to Computing,” Communications of ACM, April 2007, Vol. 50, No. 4, pp. 37 - 42.

Seoul National University Abstraction Before After

Abstraction Before After Seoul National University Abstraction Before After Jinwook Seo, “Information Visualization Design for Map Use on Future Mobile Devices (Presentation at Samsung Electronics, Dec. 8, 2008)

Instruction Set Architecture (ISA) Seoul National University Instruction Set Architecture (ISA) Application Operating System library S/W complier assembler ISA H/W

Instruction Set Architecture as an ADT Seoul National University Instruction Set Architecture as an ADT “…the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure (state) and functional behavior (operations), as distinct from the organization of the data flow and controls, the logical design, and the physical implementation.” - Amdahl, Blaauw, and Brooks, 1964

Instruction Set Architecture as an ADT Seoul National University Instruction Set Architecture as an ADT Assumptions  8 bit ISA  # of registers = 4 + PC (Program Counter)  Memory size = 64B Memory Memory 63 24 23 22 2 7 4 1 3 ·· 20 21 (add r1, r2, r3) (lw r2, 1(r0)) (sw r3, 0(r0)) (beq r0, r1, 2) (j 15) 63 24 23 22 2 7 4 1 3 ·· 20 21 (add r1, r2, r3) (lw r2, 1(r0)) (sw r3, 0(r0)) (beq r0, r1, 2) (j 15) Registers Registers add r1, r2, r3 20 2 1 r3 12 8 r2 r1 r0 PC 21 2 20 r3 12 8 r2 r1 r0 PC Before Register and Memory After Register and Memory

Instruction Set Architecture as an ADT Seoul National University Instruction Set Architecture as an ADT Assumptions  8 bit ISA  # of registers = 4 + PC (Program Counter)  Memory size = 64B Memory Memory 63 24 23 22 2 7 4 1 3 ·· 20 21 (add r1, r2, r3) (lw r2, 1(r0)) (sw r3, 0(r0)) (beq r0, r1, 2) (j 15) 63 24 23 22 2 7 4 1 3 ·· 20 21 (add r1, r2, r3) (lw r2, 1(r0)) (sw r3, 0(r0)) (beq r0, r1, 2) (j 15) Registers Registers lw r2, 1(r0) 21 2 20 r3 12 8 r2 r1 r0 PC 22 2 20 r3 7 8 r2 r1 r0 PC Before Register and Memory After Register and Memory

Instruction Set Architecture as an ADT Seoul National University Instruction Set Architecture as an ADT Assumptions  8 bit ISA  # of registers = 4 + PC (Program Counter)  Memory size = 64B Memory Memory 63 24 23 22 2 7 4 1 3 ·· 20 21 (add r1, r2, r3) (lw r2, 1(r0)) (sw r3, 0(r0)) (beq r0, r1, 2) (j 15) 63 24 23 22 8 7 4 2 1 3 ·· 20 21 (add r1, r2, r3) (lw r2, 1(r0)) (sw r3, 0(r0)) (beq r0, r1, 2) (j 15) Registers Registers sw r3, 0(r0) 22 2 20 r3 7 8 r2 r1 r0 PC 23 2 20 r3 7 8 r2 r1 r0 PC Before Register and Memory After Register and Memory

Instruction Set Architecture as an ADT Seoul National University Instruction Set Architecture as an ADT Assumptions  8 bit ISA  # of registers = 4 + PC (Program Counter)  Memory size = 64B Memory Memory 63 24 23 22 8 7 4 2 1 3 ·· 20 21 (add r1, r2, r3) (lw r2, 1(r0)) (sw r3, 0(r0)) (beq r0, r1, 2) (j 15) 63 24 23 22 8 7 4 2 1 3 ·· 20 21 (add r1, r2, r3) (lw r2, 1(r0)) (sw r3, 0(r0)) (beq r0, r1, 2) (j 15) Registers Registers beq r0, r1, 2 23 2 20 r3 7 8 r2 r1 r0 PC 24 2 20 r3 7 8 r2 r1 r0 PC Before Register and Memory After Register and Memory

Instruction Set Architecture as an ADT Seoul National University Instruction Set Architecture as an ADT Assumptions  8 bit ISA  # of registers = 4 + PC (Program Counter)  Memory size = 64B Memory Memory 63 24 23 22 8 7 4 2 1 3 ·· 20 21 (add r1, r2, r3) (lw r2, 1(r0)) (sw r3, 0(r0)) (beq r0, r1, 2) (j 15) 63 24 23 22 8 7 4 2 1 3 ·· 20 21 (add r1, r2, r3) (lw r2, 1(r0)) (sw r3, 0(r0)) (beq r0, r1, 2) (j 15) Registers Registers j 15 24 20 r3 7 8 r2 r1 r0 PC 15 20 r3 7 8 r2 r1 r0 PC Before Register and Memory After Register and Memory

Design Techniques For Each Design Technique Engineering methodology Seoul National University Design Techniques For Each Design Technique Engineering methodology Correctness criteria Evaluation methods Technology trends

Design Techniques Sequential implementation Pipelined implementation Seoul National University Design Techniques Sequential implementation Pipelined implementation Out of order execution Speculative execution Processor Processor I-cache D-cache Cache Memory Unified cache Memory Hierarchy To main memory / I/O Systems Virtual Memory Input/Output and Storage

Engineering methodology Seoul National University Engineering methodology Rule 1 : Make the (a few) common cases fast Identify & optimize Rule 2 : Make the (many) rare cases correct Plan in advance on how to enumerate them systematically

Correctness criteria Examples Seoul National University Correctness criteria Examples Pipelined execution : pipelined execution of instructions is correct if the results is as if the instructions were executed sequentially Cache memory : execution of instructions on a system with cache memory is correct if the results is as if the instructions were executed on the same system but without cache memory We’ll see a lot of as if’s

Performance Evaluation Methods Seoul National University Performance Evaluation Methods Performance types Time response time execution time Rate throughput : MIPS, MFLOPS bandwidth : Mbps Ratio relative performance (both time and rate)

Technology Trends Processor Trends DRAM Trends NAND Flash Trends Seoul National University Technology Trends Processor Trends DRAM Trends NAND Flash Trends Hard Disk Drive (HDD) Trends

Seoul National University Processor Trends

Seoul National University DRAM Trends “3D NAND Technology – Implications to Enterprise Storage Applications, 2015 Flash Memory Summit.

DRAM Market Share Seoul National University Source: https://seekingalpha.com/article/4036966-learned-micron-technology-main-competitor-samsung-electronics

DRAM Market Revenue Seoul National University Source: http://www.dramexchange.com/WeeklyResearch/Post/2/4520.html

Seoul National University NAND Flash Trends “3D NAND Technology – Implications to Enterprise Storage Applications, 2015 Flash Memory Summit.

NAND Flash Market Share Seoul National University NAND Flash Market Share Source: https://seekingalpha.com/article/4036966-learned-micron-technology-main-competitor-samsung-electronics

NAND Flash Revenue Seoul National University Source: http://worldwidegadget.blogspot.kr/2016/12/3q-2016-nand-flash-suppliers-market.html

Hard Disk Drive (HDD) Trends Seoul National University Hard Disk Drive (HDD) Trends E. Grochowski and R. E. Fontana, Jr., “An Analysis of Flash and HDD Technology Trends,” Flash Memory Summit 2011. Disk density: 1.50x - 1.60x per year (4x in three years)

Recent HDD Trends Cost per GB Seoul National University Source: https://www.backblaze.com/blog/hard-drive-cost-per-gigabyte/.

Pitfalls of Computer Technology Forecasting Seoul National University Pitfalls of Computer Technology Forecasting DOS addresses only 1 MB of RAM because we cannot imagine any applications needing more.” Microsoft, 1980 “640K ought to be enough for anybody.” Bill Gates, 1981 “Computers in the future may weigh no more than 1.5 tons.” Popular Mechanics “I think there is a world market for maybe five computers.” Thomas Watson, IBM Chairman, 1943 “There is no reason anyone would want a computer in their home.” Ken Olsen, DEC founder, 1977 “The 32-bit machine would be an overkill for a personal computer.” Sol Libes, ByteLines From Prof. Behrooz Parhami’s lecture notes

Comparison to Other Technology Trends Seoul National University Comparison to Other Technology Trends