S-RCAT(Sphere-shaped-Recess-Channel-Array-Transistor) Technology for 70nm DRAM feature size and beyond J.Y.Kim and Kinam Kim, et all (Samsung Electronics) 2005 Symposium on VLSI Technology Wookhyun Kwon

This is a story about…. How to solve a difficult problem of DRAM technology. It was a great idea like the Egg of Columbus. Egg of Columbus

Vstorage = Qc / Cstorage DRAM Operation Storage Capacitor Bit Line Gate Vstorage = Qc / Cstorage Key of DRAM operation How long the storage node maintain the stored charge?  Target >100msec

Motivation: Data Retention Time Issue Scaling Rule Parameter Scaling Factor Channel Length (Lch) 1/K Tox Nsub K Xj Xj DIBL GIDL Junction Leakage Channel length scaling is a necessity for small cell size. But… Short channel  Enhance DIBL Thin gate oxide  Enhance GIDL High Nsub & Shallow junction depth  Increase junction leakage. We could not obtain sufficient data retention time near 100nm tech.  How to solve this problems?

Suggested Solutions High Tech. Increasing Fab. Cost! High-K material (for Gox and Storage cap.) Increasing Cs Thick gate oxide SOI (Silicon on Insulator) Reduce DIBL Increasing Fab. Cost!

Simplest way is… Making a long channel length in same area. Planar RCAT Xj RCAT (Recessed Channel Array Transistor) DRAM (512Mb, ’03) Long effective channel length & Deep junction depth. Improve refresh characteristics

1st Generation RCAT RCAT Scaling But, by increasing recess depth Tech 110nm 90nm 80nm 70nm Recess Depth 150nm 170nm 190n, 200nm Vth 1.1V 1.2V Recess Depth But, by increasing recess depth Sharp curvature problem  Gox reliability Uniformity Neck part enlargement Chemical Dry Etching

2nd Generation RCAT= S-RACT Poly Void S-RCAT (Shere-shaped RCAT) DRAM (2Gb, ’03) Larger effective channel length Larger curvature  small vertical field  suppress GIDL Small junction depth

Process Sequence Key Process Isotropic Dry Etching Oxide spacer Key Process Oxide spacer for protecting Si-neck-enlargement Isotropic dry etch (Low power silicon etch) Steam RTP oxidation or Plasma oxidation

Electrical Characteristics Good uniformity of Vth (250mV) Improving DIBL (80mV  40mV) Smaller junction leakage Improving data retention time

DRAM Cell Size Trend 46nm (Half pitch) 6F2 S-RCAT S-RCAT We are now here! Who? Source (IRTS 2006) 46nm (Half pitch) 6F2 S-RCAT

Summary In DRAM technology, the data retention was the big problem. Using RCAT structure, we could solve the problem by increasing the effective channel length in same cell size. It don’t need a significant high-technology. The great idea comes from very simple idea.

Thank you. Questions?

Reference

More Scaling S-RCAT has a good scalability to sub-50nm. Below 40nm, the isolation between balls (C ) will be a limiter. for further scaling below, another breakthrough in technology is needed.

4F2 with Vertical Transistor

6F2 Architecture 25% cell size reduction The 6F2 architecture have Diagonal direction of channel Non-planar channel (RCAT) Source (Samsung)