EMC of ICs Practical Trainings

Summary IC-EMC – Reference Basic concepts Emission Signal integrity Ex. 1. FFT of typical signals Ex. 2. Transient current estimation Emission Ex. 3. di/dt noise Ex. 4. PDN modeling Signal integrity Ex. 5. Impedance mismatch Susceptibility Ex. 6. Estimation of susceptibility level June 18

IC-EMC - Simulation flow IC-EMC schematic Editor (.sch) IC-EMC model libraries WinSPICE compatible netlist generation (.cir) WinSPICE simulation Measurement import IC-EMC Post-processing tools (emission, impedance, S-parameters, immunity) Output file generation June 18

IC-EMC – Most Important Icons Open schematic (.sch) Build SPICE netlist (.cir) Save schematic (.sch) Spectrum analysis Delete symbols Near field emission simu. Copy symbols Immunity simulation Move symbols Time domain analysis Rotate symbols Impedance simulation Flip symbols S parameter simulation Add Text line Ibis file editor Add a line Parametric analysis View electrical net Symbol palette Zoom in/out View all schematic June 18

IC-EMC – Link to WinSpice Click on WinSPICE.exe Click File/Open to open a circuit netlist (.cir) generated by ic-emc. IC-EMC main commands (text line): Simulation command Command line Parameters Transient simulation .tran 0.1n 100n step + stop time DC simulation .DC Vdd 0 5 0.1 source + start + stop + step Small signal freq. analysis .AC DEC 100 1MEG 1G sampling + nb points + start + stop Load SPICE library .lib 65nm.lib Path and file name June 18

Exercise 1. FFT of typical signals Create the schematic Set the source generator Transient simulation FFT by IC-EMC Simulate the FFT of a sinus and a square signal 6 June 18

Exercise 1. FFT of typical signals FFT of a sinus source Set the voltage generator properties: Frequency = 1 GHz Amplitude = 1 V Electrical model in Ex1-FFT-sinus.sch. Ex1-FFT-sinus.sch 7 7 June 18

FFT of a sinus source Exercise 1. FFT of typical signals Type the simulation command: .tran 1n 50n Simulate the response in time domain. Compute the FFT. Does the FFT result correlate with theoretical result ? June 18

FFT of a square current source Exercise 1. FFT of typical signals FFT of a square current source Set the generator properties For example: Period = 10 n, PW = 4 n, Tr = 1n, Tf = 1 n V0 = 0 V, V1 = 1 V Electrical model in Ex1-FFT-Pulse.sch. Ex1-FFT-Pulse.sch June 18

FFT of a square source Exercise 1. FFT of typical signals For a trapezoidal signal (Tr=Tf) For a square signal (Tr=0) June 18

Exercise 2. Transient current estimation Standard cell inverter in CMOS technology Typical load capacitance Observe in time domain the current through Vss. Electrical model in Ex2-transient_inverter.sch. Ex2-transient_inverter.sch June 18

Exercise 2. Transient current estimation Time domain simulation Adjust scales (Autofit and zoom on time axis) June 18

Exercise 2. Transient current estimation What is the influence of the load capacitance (1 fF to 1 pF) ? Ipeak Rise time Cload Cload June 18

Exercise 3. di/dt noise Estimate the voltage bounce on Vdd and Vss pins of the core when it is mounted in a QFP 64. The core clock is 20 MHz. Core noise margin ? Electrical model in Ex4-didt_noise.sch. Voltage fluctuations on Vdd or Vss node is equal to +/- L*di/dt = 6 nH*600 mA/150 ps = +/- 24 V. The circuit is supplied under 1.2 V  the voltage fluctuation is 20 times larger than the nominal power supply ! However, this evaluation is unrealistic, because it supposes that all the current consumed by the circuit will flow through the package inductance. The circuit contains intrinsic capacitor which acts as a decoupling capacitor and reduce the voltage bounces. Ex4-didt_noise.sch June 18

Exercise 3. di/dt noise June 18

Exercise 4. PDN Modeling DSPIC Z(f): find an R,L,C model Impedance vs. Freq DSPIC Z(f): find an R,L,C model Tune to measurement file: Electrical model in Ex7-PDNmodel.sch. z11-dspic-vdd_10-vss_9.z June 18

Exercise 4. PDN Modeling z11-C1nF_0603.z 1nF discrete capacitance for DPI Impedance vs. Freq June 18

5 V power supply + filtering Exercise 5. Impedance Mismatch Let’s consider the following link between 2 digital inverters. No matching is placed at each termination. The digital inverters are 74AHCT04, from NXP. The IBIS file ahct04.ibs is given. Build a SPICE model to evaluate the signal integrity at each termination of this digital link. Section of the line Top layer (signal line + power) 35 µm W = 0.36 mm 1.6 mm FR4 (εr = 4.5) 35 µm Bottom layer – GND plane 5 V power supply + filtering 2nd inverter: input driver 1st inverter: output driver 1 MHz square signal 10 cm 120 Ω microstrip line June 18

Exercise 5. Impedance Mismatch From IBIS file, propose an equivalent model for input and output driver. “File > Load IBIS” ahct04.ibs Package outline Input Output Functional diagram June 18

Exercise 5. Impedance Mismatch Measured I(V) charac. Of output buffer Proposed models for input and output driver. IBIS_buffer_out_carac_IV.sch Measured I(V) charac. Of input buffer IBIS_input_buffer_IV.Sch June 18

Exercise 5. Impedance Mismatch Verify the theoretical characteristic impedance of the microstrip line (“Tools > Interconnect Parameters”). The following S11 measurements have been done: Line open (zin-line120-open.s1p) Line loaded by 51 Ω resistor (zin-line120-load51.s1p) Line loaded by 120 Ω resistor (zin-line120-match.s1p) Propose an equivalent model for the line. zin-line120-open.s1p zin-line120-match.s1p June 18

Exercise 5. Impedance Mismatch Output driver Build the complete electrical model of the digital link. Simulate the transient response of signal at each termination of the link. Validate your model from measurements: Rising waveform at output driver (rw_out_no_match.tran) Falling waveform at output driver (fw_out_no_match.tran) Rising waveform at input driver (rw_in_no_match.tran) Falling waveform at input driver (fw_in_no_match.tran) Input driver June 18

Exercise 5. Impedance Mismatch Input driver – R matching Two solutions are proposed to improve signal integrity: Place two 120Ω resistors at both line terminals Place one 120Ω resistor at output driver side, one 120Ω resistor and a serial 4.7 pF capacitor Test the effect of both solutions. Validate your models from measurements: Rising waveform at output driver (rw_out_matchR.tran and rw_out_matchRC.tran) Falling waveform at output driver (fw_out_matchR.tran and fw_out_matchRC.tran) Rising waveform at input driver (rw_in_matchR.tran and rw_in_matchRC.tran) Falling waveform at input driver (fw_in_matchR.tran and fw_in_matchRC.tran) Input driver – RC matching June 18

Exercise 6. Estimation of susceptibility level A RF generator produces a conducted disturbance which is injected on a 200 Ω load, though a directional coupler. Ex9-RloadSusc.sch Electrical model in Ex9-RloadSusc.sch. Due to the small size of ICs, the susceptibility of an IC to EMI is usually characterized by conducted RF disturbances rather than radiated disturbances. The conducted tests are more repeatable and efficient than radiated tests. In conducted tests such as DPI tests, a conducted disturbance is provided to a circuit pin by cables and PCB tracks, which act like antennas which couple a radiated disturbance. The conducted disturbances represent the unwanted RF-energy coupled on cable harness and PCB tracks. The susceptibility level is usually given in term of forward power delivered to the circuit. The susceptibility level depends on the circuit and pin configuration (i.e. filtering, decoupling on the pin, impedance of the pin). Estimate the forward power to induce 1 V across the load over the frequency range 10 MHz – 1 GHz. June 18

Exercise 6. Estimation of susceptibility level Launch Susceptibility tool Configure the RF disturbance and launch SPICE simulation Configure the voltage criterion and extract susceptibility threshold Display the susceptibility threshold Typical forward power ranges from 10 dBm to 30 dBm. Corresponding to the specification of immunity level given by IEC 62132-3 – DPI standard. June 18

Exercise 6. Estimation of susceptibility level June 18

Exercise 6. Estimation of susceptibility level Validity of the result ? Pforward = 6 dBm Vinc = Vload /(1+S11) et S11 = (Zload-Zc)/(Zload+Zc) = (200-50)/(200+50) = 0.6 Vinc = 1/1.6 = 0.625 V Pinc = Vinc²/Zc = 0.625²/50 = 7.8 mW = 9 dBm  Pinc rms = Pinc/2  Pinc rms = Pinc – 3 dB = 6 dBm June 18

Synthesis of Exercises 1 to 5 What did we learn ? June 18