ECE2030 Introduction to Computer Engineering Lecture 4: CMOS Network Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech

CMOS Inverter Connect the following terminals of a PMOS and an NMOS Gates Drains Vdd Gnd Vout Vin Vin = HIGH Vout = LOW (Gnd) ON OFF Vdd Gnd Vout Vin Vin = LOW Vout = HIGH (Vdd) ON OFF Vdd PMOS Vin Vout Ground NMOS

CMOS Voltage Transfer Characteristics Vdd PMOS Vin Vout NMOS Gnd OFF: V_GateToSource < V_Threshold LINEAR (or OHMIC): 0< V_DrainToSource < V_GateToSource - V_Threshold SATURATION: 0 < V_GateToSource - V_Threshold < V_DrainToSource Note that in the CMOS Inverter  V_GateToSource = V_in

Pull-Up and Pull-Down Network CMOS network consists of a Pull-UP Network (PUN) and a Pull-Down Network (PDN) PUN consists of a set of PMOS transistors PDN consists of a set of NMOS transistors PUN and PDN implementations are complimentary to each other PMOS  NOMS Series topology Parallel topology Vdd PUN OUPTUT …. I0 PDN I1 In-1 Gnd

PUN/PDN of a CMOS Inverter Vdd A B 1 Z Pull-Up Network A B A B Z 1 Pull-Down Network Gnd A B 1 Combined CMOS Network CMOS Inverter

Gate Symbol of a CMOS Inverter Vdd A B A B B = Ā Gnd CMOS Inverter

PUN/PDN of a NAND Gate Vdd Pull-Up Network B A Pull-Down Network C A B 1 Z Vdd Pull-Up Network B A A B C Z 1 Pull-Down Network C A B

PUN/PDN of a NAND Gate Vdd Pull-Up Network B A Pull-Down Network C A B 1 Z Vdd Pull-Up Network B A A B C Z 1 Pull-Down Network C A B A B C 1 Combined CMOS Network

NAND Gate Symbol Truth Table Vdd A B C 1 B A C A A C B B

PUN/PDN of a NOR Gate Vdd Pull-Up Network A B Pull-Down Network C B A 1 Z Vdd Pull-Up Network A A B C Z 1 B Pull-Down Network C B A

PUN/PDN of a NOR Gate Vdd Pull-Up Network A B Pull-Down Network C B A 1 Z Vdd Pull-Up Network A A B C Z 1 B Pull-Down Network C B A A B C 1 Combined CMOS Network

NOR Gate Symbol Vdd Truth Table A B C 1 A B C A C B A B

How about an AND gate Vdd A B Gnd C NAND Inverter C = A B A B C

An OR Gate A B Vdd Gnd C Inverter NOR A B C

What’s the Function of the following CMOS Network? B C Z 1 Vdd C Pull-Up Network A B C 1 Z Pull-Down Network A B C 1 Combined CMOS Network Function = XOR

Yet Another XOR CMOS Network Vdd A B C Z 1 Pull-Up Network A B C 1 Z C Pull-Down Network A B C 1 Combined CMOS Network Function = XOR

Exclusive-OR (XOR) Gate Vdd Truth Table A B C 1 C A C B

How about XNOR Gate How do we draw the corresponding CMOS network Truth Table A B C 1 How do we draw the corresponding CMOS network given a Boolean equation? A C B

How about XNOR Gate Vdd C XOR Inverter Truth Table A B C 1 A C B

A Systematic Method (I) Start from Pull-Up Network Each variable in the given Boolean eqn corresponds to a PMOS transistor in PUN and an NMOS transistor in PDN Draw PUN using PMOS based on the Boolean eqn AND operation drawn in series OR operation drawn in parallel Invert each variable of the Boolean eqn as the gate input for each PMOS in the PUN Draw PDN using NMOS in complementary form Parallel (PUN) to series (PDN) Series (PUN) to parallel (PDN) Label with the same inputs of PUN Label the output

A Systematic Method (II) Start from Pull-Down Network Each variable in the given Boolean eqn corresponds to a PMOS transistor in PUN and an NMOS transistor in PDN Invert the Boolean eqn With the Right-Hand Side of the newly inverted equation, Draw PDN using NMOS AND operation drawn in series OR operation drawn in parallel Label each variable of the Boolean eqn as the gate input for each NMOS in the PDN Draw PUN using PMOS in complementary form Parallel (PUN) to series (PDN) Series (PUN) to parallel (PDN) Label with the same inputs of PUN Label the output

Systematic Approaches Note that both methods lead to exactly the same implementation of a CMOS network The reason to invert Output equation in (II) is because Output (F) is conducting to “ground”, i.e. 0, when there is a path formed by input NMOS transistors Inversion will force the desired result from the equation Example F=Ā·C + B: When (A=0 and C=1) or B=1, F=1. However, in the PDN (NMOS) of a CMOS network, F=0, i.e. an inverse result. Revisit how a NAND CMOS network is implemented Inverting each PMOS input in (I) follow the same reasoning

Example 1 (Method I) Vdd In parallel In series (1) Draw the Pull-Up Network

Example 1 (Method I) Vdd In parallel A B In series C (2) Assign the complemented input

Example 1 (Method I) Vdd In parallel A B In series C (3) Draw the Pull-Down Network in the complementary form A C

Example 1 (Method I) Vdd In parallel A B In series C (3) Draw the Pull-Down Network in the complementary form A C B

Example 1 (Method I) Vdd In parallel A B In series C F Label the output F A C B

Example 1 (Method I) Vdd In parallel A B In series C Truth Table F A C 1 A C B

Drawing the Schematic using Method II Vdd A B C F A C B This is exactly the same CMOS network with the schematic by Method I

An Alternative for XNOR Gate (Method I) Vdd Truth Table A B C 1 C A C B

Example 3 A D A B D C Start from the innermost term

Example 3 A C A B D C Start from the innermost term A D

Example 3 A B D C Start from the innermost term B A D A C

Example 3 Vdd A B D C Pull-Up Network Start from the innermost term F Pull-Down Network A C

Example 4 A B D C Vdd F E Pull-Down Network Pull-Up Start from the innermost term

Another Example How ??