This is a test Preliminary study for a csa front-end in 180nm CMOS technology for Monolithic pixel sensors R. Ballabriga CERN, EP Department 1211 Geneva 23 Switzerland Thanks to M. Munker and T. Kugathasan

Outline Design considerations One stage front-end Summing front-end This is a test Outline Design considerations One stage front-end Summing front-end Fundamental limits Summary and conclusions

Design considerations

Design considerations (CLIC TD) This is a test Design considerations (CLIC TD) Requirements for a monolithic chip for the CLIC silicon tracker [1]: Single point resolution in one dimension ≤7 𝜇𝑚 Length of short strip/long pixel: 1 −10 𝑚𝑚 10 ns time slicing, with a counter depth of 8-bits (Time of Arrival) No multi-hit capability Energy measurement (Time over Threshold): 5-bits resolution (Hit resolution / time walk correction) Design of a cell measuring 30x300 𝜇𝑚2 (first prototype) The cell is segmented into sub-pixels (~30 𝜇𝑚 pitch) to ensure prompt charge collection [1] D. Dannheim, A. Nürnberg: Requirements for the CLIC tracker readout (CLICdp-Note-2017-002) https://cds.cern.ch/record/2261066

Electronics design considerations This is a test Electronics design considerations MIP Signal in thin Si layer ~50e-/h+/mm, 30mm depleted region i.e. 1500e- NMOS transistors biased with VB=-6V (the modelling could not be accurate) Nwell-Pwell capacitance not modelled Pixel leakage current ~100fA (before irradiation), 2pA (after irradiation 1012 neq/cm2) and 1nA (1015 neq/cm2) Total Ionizing Dose (TID) effects are a typical case of cumulative effects. The ionization dose is deposited by particles passing through the materials constituting the electronic devices. This happens during the whole time the device is exposed to radiation. The same is true for displacement damage. TID is the measurement of the dose, that is the energy, deposited in the material of interest by radiation in the form of ionization energy. The unit to measure it in the International System (SI) is the Gray, but the radiation effects community still uses most often the old unit, the rad. One should get used to both, because the dosimetry people speak about Gray, whilst electronic engineers working on the effects speak about rad. Luckily, the equivalence between the two is easy to remember: 1 Gray (Gy) = 100 rad Displacement damage is not measured in any unit, just in its effects on the devices. The displacement damage is expressed in terms of the particle fluence, in particles/cm2. Non Ionizing Energy Loss (NIEL) Thanks: T. Kugathasan, M. Munker

This is a test Why CSA? Linearity (Amplitude and ToT)

1-stage front-end

Classical Krummenacher Amplifier input capacitance (detector+parasitics+input transistor) feedback capacitance For noise (series thermal): Minimize cf and ci Does not depend on the transconductance (increasing gm decreases noise but also increases the bandwidth) For timing: Maximize gm

Classical Krummenacher Amplifier Noise due to M1g feedback capacitance gm(M1g) gm(M2a) gm(M1g)/gm(M2a)=2 (if transistors are in weak inversion)

Classical Krummenacher Amplifier This is a test Classical Krummenacher Amplifier CF=1fF (min value limited by the architecture) CD=2fF (detector and interconnections) IPREAMP=50nA (10mW/cm2 (preamp only/30um pixels)) (5.6mW/cm2 (preamp only/40um pixels)) Gain=160mV/ke- Noise=35e- r.m.s Unequalized threshold=70e- r.m.s. Equalized (3bits)=15e- r.m.s. Equalized (4bits)=7e- r.m.s. Minimum detectable charge=215e- Slope=9.2MV/s (Jitter=noise/slope=0.8ns) 50nA/pixel 111111pixels/cm2 (30um pixels) 5.55mA/cm2 10mW/cm2 62500pixels/cm2 (40um pixels) 3.125mA/cm2 5.625mW/cm2 10ns

Summing front-end

Schematic 1 CLICTD strip

Schematic 1 CLICTD strip This is a test

Simulations schematic 1 CLICTD strip CF=0.5fF CD=2fF IPREAMP=50nA, ISUMMINGSH=50nA Gain=230mV/ke- Noise1CH=24e- r.m.s Unequalized threshold=50e- r.m.s. Equalized (3bits)=11e- r.m.s. Equalized (4bits)=5.5e- r.m.s. Minimum detectable charge=160e- Slope=2.5MV/s (Jitter=noise/slope=2.3ns) 10ns When doing the summing of 10 channels, the noise multiplies x3 There are optimizations to be done in the circuit (gain factors, time constants in the circuit processing the reconstructed signal, timing, linearity)

Fundamental limits

This is a test Fundamental limits The summing stage can be designed to provide shaping/filtering* CD=2E-15; %Detector capacitor [F] CF=1E-15; %Feedback capacitor [F] W=1E-6; %W is the transistor Width [m] L=0.18E-6; %L is the transistor Length [m] COX=8.3E-3; %COX is the capacitance per unit area (F/m2) ID=50E-9; %ID is the drain current [A] IS=1; %IS is the specific current (normalized) sf=1.2; %Slope factor for the input transistor N=1; %Shaper order KA=3E-24; %Flicker noise constant ILEAK=2E-12; %Detector leakage current IFBK=200E-12; %Current for the reset of the preamplifier output voltage Series thermal Series flicker Parallel Negligible Shaping time (ts)

Fundamental limits Series thermal Series flicker Parallel This is a test Fundamental limits CF=1E-15; %Feedback capacitor [F] W=1E-6; %W is the transistor Width [m] L=0.18E-6; %L is the transistor Length [m] COX=8.3E-3; %COX is the capacitance per unit area (F/m2) ID=50E-9; %ID is the drain current [A] IS=1; %IS is the specific current (normalized) sf=1.2; %Slope factor for the input transistor N=1; %Shaper order KA=3E-24; %Flicker noise constant ILEAK=2E-12; %Detector leakage current IFBK=200E-12; %Current for the reset of the preamplifier output voltage Increase gm Decrease CIN Decrease IFBK Series thermal Series flicker Parallel Negligible Shaping time (ts)

Fundamental limits Series thermal Series flicker Parallel This is a test Fundamental limits CF=1E-15; %Feedback capacitor [F] W=1E-6; %W is the transistor Width [m] L=0.18E-6; %L is the transistor Length [m] COX=8.3E-3; %COX is the capacitance per unit area (F/m2) ID=50E-9 (1) 200E-9 (2); %ID is the drain current [A] IS=1; %IS is the specific current (normalized) sf=1.2; %Slope factor for the input transistor N=1; %Shaper order KA=3E-24; %Flicker noise constant ILEAK=2E-12; %Detector leakage current IFBK=200E-12; %Current for the reset of the preamplifier output voltage Increase gm (IPREAMP x4) (1) (2) Trade off Energy resolution vs Flux Series thermal Series flicker Parallel 200pA gmFB=6.4nS -> RFB=156MOhm Tau=RFB*CFB=156x10^6 x 1E-15=156ns Negligible Shaping time (ts)

Summary and conclusions

Summary and conclusions This is a test Summary and conclusions A preliminary study is presented about using a CSA for the readout of the CLICTD Linear system for the summing The small input capacitance potentially allows very low noise and low power consumption (w.r.t. other monolithic technologies) An architecture suitable for the CLICTD (with signal summing from different collection electrodes) was shown. Still room for optimization. Gain factors Linearity Time constants Complete simulation with 10 channels (Noise x3) The simulation of the fundamental limits show that a noise about 15e- could be achieved with ~20ns shaping time and IIN=200nA Non Ionizing Energy Loss (NIEL)

Additional

Energy deposition in THIN Si deposit / µm is decreasing Bak et al. Nucl. Phys. B288 (1987) 681 HEIJNE GRUHN e CALC --- LIMIT/MEAN 360 eV/µm ------ e-h PAIRS PER µm + 220 eV 25µm eV/µm 90 -- 60 -- 100 -- 80 -- 70 -- PEAK WIDTH Heijne CERN 83-06 (1983) 30 Meroli et al. J. Instr 6 (2011) P06013 < 1mm BINDING of ELECTRONS causes deviation from Landau distribution: shift+widening values for VERY thin devices: + ~55 e-h pairs/µm + 220 eV 25µm