AIDA ASIC review Davide Braga Steve Thomas ASIC Design Group

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Presentation transcript:

AIDA ASIC review Davide Braga Steve Thomas ASIC Design Group 14 January 2009

Top level

Analogue input and bias reference

Digital block and control register

Analogue outputs

Remaining work: Time-scale: Layout of bias pads Wiring between control register and DACs Connection of mux output amplifier Power supply distribution, to minimise resistance Top level checks, including metal coverage and antenna rules Top level simulation, with final schematic (compatible with layout) Update of documentation (project spec, pad definitions, waveforms) Time-scale: Design submission on 26 January Request for quotation 15 January? [need to specify exact die size and chip numbers]