INFN Pavia and University of Bergamo FSSR2 chip: noise optimization of the analog front-end for the readout of long strip detectors in SuperB SVT Valerio Re INFN Pavia and University of Bergamo SuperB Workshop Frascati, December 1 – 4, 2009 V. Re SuperB Workshop 02/12/2009

FSSR2 Fast, data driven readout architecture, with no analog storage, with large output bandwidth FSSR2, designed for the BTeV Forward Silicon Tracker (Pavia/Bergamo-Fermilab), has the right features: Mixed-signal integrated circuit for the readout of silicon strip detectors (selectable shaper peaking time: 65-85-125 ns) TSMC 0.25 µm CMOS tech. with enclosed NMOS  Rad. Hard 128 analog channels, sparsified digital output with address, timestamp, and pulse height information for all hits Architecture designed to run with 132 ns bunch crossing (timestamp granularity = BCO clock = 7.6 MHz), readout clock @ 70 MHz  840 Mb/s output data rate. For more details on FSSR2 see for example: V. Re et al., “FSSR2, a Self-Triggered Low Noise Readout Chip for Silicon Strip Detectors”, 2005 IEEE Nuclear Science Symposium Conference Record V. Re: “First prototype of a silicon microstrip detector with the data-driven readout chip FSSR2 for a tracking-based trigger system” , presented @ 10th Pisa Meeting on Advanced Detectors, La Biodola (Isola d’Elba), May 21 – 27, 2006 V. Re SuperB Workshop 02/12/2009

Analog channel (evolution of AToM) Preamplifier Programmable Gain To 3-bit Flash ADC Cf1 Programmable Baseline Restorer Cf Bias Hit/NoHit Discriminator + Shaper Threshold circuit Gf Comparator CD Kill BLR Single-ended/ Differential conversion - - CR-(RC)2 Vth + CAC Cinj Test Input (from Internal Pulser) Programmable Peaking time (65 ns - 125 ns) Threshold DAC (chip wide) V. Re SuperB Workshop 02/12/2009

However, ENC is well below the spec value of 1000 e rms at CD = 20 pF. FSSR2 analog channels Preamplifier NMOS input device, W/L = 1500/0.45, ID = 500 mA The BLR improves the threshold dispersion (AC coupling), but increases noise by 15% However, ENC is well below the spec value of 1000 e rms at CD = 20 pF. V. Re SuperB Workshop 02/12/2009

Noise forecast for SVT external layers From L. Bosisio slides, 17/9/09, SuperB SVT meeting: Worst case: SVT external layers, Phi-side layer5. Strips 37 cm long. C = 1.5 pF/cm R = 1 W/cm CD = 55 pF, RS = 370 W Expected ENC = 1400 e rms at tP = 125 ns and no BLR (best case for FSSR2, may be unnecessary if occupancy is low), neglecting noise from series strip resistance and parallel noise (detector leakage and bias resistor) V. Re SuperB Workshop 02/12/2009

How can FSSR2 noise be improved and optimized for FSSR2 external layers? Better capacitive matching  Optimize input NMOS gate width W (FSSR2 was optimized for CD = 20 pF) Reduce channel thermal noise  Increase drain current ID (power dissipation constraints?)  Increase signal peaking time tP (occupancy constraints?) V. Re SuperB Workshop 02/12/2009

ENC estimates Based on measured noise parameters for transistors in the 0.25 mm TSMC technology and on noise equations valid for all inversion regions V. Re SuperB Workshop 02/12/2009

ENC equation thermal noise of preamplifier input NMOS thermal noise of the distributed resistance RS 1/f noise of preamplifier input NMOS Parallel noise from detector leakage current and bias resistor V. Re SuperB Workshop 02/12/2009

Better capacitive matching Keep tP = 125 ns, ID = 500 mA (as is in FSSR2), change gate width W of input NMOS)  very little gain (S/N =12 with 300 mm silicon) FSSR2 as is FSSR2 as is V. Re SuperB Workshop 02/12/2009

Increase drain current in input transistor Keep tP = 125 ns, W/L = 1500/0.45 (as is in FSSR2), increase ID  not that big gain, even at high currents FSSR2 as is V. Re SuperB Workshop 02/12/2009

Increase peaking time S/N = 26 at tP = 1 ms (no BLR) Keep ID = 500 mA, W/L = 1500/0.45 (as is in FSSR2), increase tP  large gain, possible upper limit set by occupancy (parallel and 1/f noise do not seem be a severe limitation) FSSR2 as is S/N = 26 at tP = 1 ms (no BLR) V. Re SuperB Workshop 02/12/2009

And what about striplets in Layer 0? To handle with background rates without degrading efficiency, it may be necessary to decrease the peaking time with respect to present minimum FSSR2 value of 65 ns Striplets capacitance + strays V. Re SuperB Workshop 02/12/2009

Upgraded FSSR2 for fast readout of Layer 0 striplets Assuming signal = 16000 e- (Si 200 um thick), S/N = 22 at tP = 25 ns (18-20 with BLR) ENC = 720 e rms at tP = 25 ns Rs = Lfanout *2 /cm + Ldet*20 /cm=55  V. Re SuperB Workshop 02/12/2009

Conclusions The noise performance of FSSR2 was optimized for CD = 10 pF – 50 pF, making it suitable for the readout of long strips and striplets in SuperB SVT In the analog section, the selectable peaking time values should be extended both to short tP (Layer 0 striplets) and to long tP (long strips in external layers) V. Re SuperB Workshop 02/12/2009

Backup V. Re SuperB Workshop 02/12/2009