Irradiation test results for SAMPA MPW1 and plans for MPW2 irradiation tests Sohail Musa Mahmood 23.03.17

Radiation level at ALICE during RUN 3 Fig : Rate of hadrons with energy of >20MeV for a Pb-Pb collision rate of 50 kHz [1] Contour plot based on monte carlo simulations using FLUKA for RUN 3. Single Event Effects High Energy Hadrons (HEH) are main source of SEEs in TPC. Estimated Flux (HEH) ~3.4kHz/cm^2. (10 x). . It is also comparable to the fluxes experienced by space electronics when passing through the South Atlantic Anomaly This may lead to Single Event Upset (SEU) Single Event Transient (SET) Single Event Latch-up (SEL) SEEs may result in the complete system failure in the readout for the TPC detector, which in turn can require the complete ALICE experiment to be stopped and reconfigured in order to remove and correct this situation. High Energy Hadrons (HEH) are the main source of Single Event Effects (SEE) in TPC readout electronics (~3.4kHz/cm^2) . [1]: ALICE TDR for the Upgrade of the ALICE Read-out & Trigger System, LHCC-TDR-015, 3. July 2014

Single Event Effects in Electronics A Single Event Effect occurs when a highly energetic particle strikes sensitive regions of an electronic device disrupting its correct operation. VDD 1 Trigger parasitic PNPN structure Heavy charged particle Qdeposited > Qcritical => 1  0 Direct path between power and ground. High current state. Permanently damaged, if not power cycled. Single Event Latchup (SEL): High LET particles trigger a parasitic PNPN structure which creates a potentially high current state which in turn can lead to permanent damage unless current limitation protects the device (requires power cycle). -SEL may cause permanent damage to the device. If the device is not permanently damaged, power cycling of the device (off and back on) is necessary to restore normal operation. -An example of SEL in a CMOS device occurs when the passage of a single particle induces the creation of parasitic bipolar (p-n-p-n) shorting of power to ground. Single Event Upset (SEU) in SRAM Single Event Latch-up (SEL) in CMOS

SAMPA MPW1 irradiation tests 1st Prototype (DUT) 159 MeV 429 cm Proton beam 180 MeV Energy SAMPA MPW1 irradiation tests were conducted in Uppsala April 2015 using the Proton beam (Fluence ~2e11 p/cm2 ). 38mm x 38 mm graphite collimator Blue Hall @ The Svedberg Laboratory (TSL)

Irradiation test setup for MPW1 3 Pre-amplifiers 3 Analog to Digital Converters (ADCs) Shift register (15000 flip flops) 3 Digital Signal Processing channels (DSPs) For data storage: Only registers (FFs) Current monitoring board FPGA-kit to control shiftregister Single Event Latch-up (SEL): Monitoring currents on analog and digital power supply. Single Event upset (SEU) in shiftregister FPGA-kit controls shiftregister (pattern / clock) over HSMC cable. Input pattern 01010101.

MPW1 irradiation test results for shift register The first results showed a linear behavior between number of particles hitting DUT (Fluence) and number of errors (SEUs). σ [SEU] cm^2/bit = 1E−09 15000 = 6.67E-14 # of flip flops Only 15000 FFs

Impact of irradiation test results on the full readout system for TPC detector. No SEL was observed during 1st irradiation tests, with 1.3 hr beam time and fluence of 1.7e11 p/cm2 . SEE/s = σ x # bits x Flux (TPC) x [#chips] σ [FFs] = 1E-13 cm2/bit σ [SEL] < 6E-12 cm2 FLUX (TPC) = 3400 p/cm2/s Total SAMPAs = 17000 SEE/s MTB SEE #chips 1 17000 Flip-flop (55k) 1.87e-5 0.32 15 hr 3 s SEL < 2e-8 < 3.5e-4 > 13.5 khr > 48 min

New features are added to SAMPA MPW2 9 mm 32 ADCs 3 Pre-amplifiers 5 mm 32 Pre-amplifiers 5 mm 9 mm 3 ADCs 3 DSP channels For data storage: Only registers (FFs) 32 DSP channels For data storage: 125k registers (FFs) 2.5 Mbit SRAM Memory 32 OUTPUT DRIVERS Ball Grid Array (BGA) package

SEU mitigation techniques in MPW2 Tripple Modular Redundancy (TMR) TMR works, if the SEU happens in one of the triplicated modules, or on the data path. TMR fails, if SEUs occur in two out of three modules, or the SEU occur in the voter. 62% (35 k) registers are TMR protected (critical configuration/control registers). Hamming Error Correction Code The header packet is protected against SEU with Hamming error correction code which performs correction of single error and detection of double error (SECDED). The packet headers are equipped with a Hamming error correction code which enables correction of one error and detection of two errors in the header. The Hamming code is added to the header before it is written to the ringbuffer memory and it is checked again when it is read out of the ringbuffer, before it is sent to the serial links

SEU tests for MPW2 Registers (FFs) Hamming correction SRAM Memory

Plans for MPW2 irradiation tests Single Event Latchup Current monitoring for all power domains (2 Analog, 1 ADC, 2 Digital). Longer runs to increase statistics. At least 3 devices for minimum probing of device-to-device variation. Total Ionizing Dose (TID) Monitor the output voltage of power regulators. Monitor the Baseline from the analog part. Monitor the frequency of Ring Oscillator (test structure in MPW2). Proton beam 190 MeV @ KVI on 29.03 Questions?

Back up

During irradiation test, the rate at which the protons strikes the DUT (Flux) and the irradiating time is important. Flux: ~6e6 – 6e7 p/cm2/s Total Fluence: ~2e11 p/cm2 (~12kRad)

SEU test setup for MPW1 (8-bit SR) CLK IN POS 1 POS 2 POS 3 POS 4 POS 5 POS 6 POS 7 POS 8 OUT 1 1 1 2 1 1 3 1 4 1 5 Bit flip from 1 to 0 6 1 7 8 1 1 1 9 1 10 1 1

MPW1 @ TSL: Results shift register SEU (10) SEU (01) SEU (Tot) Fluence [p/cm2] Cross setion/bit [cm2] RUN 1 2 4 6 5.8E+9 6.9E-14 RUN 2 23 47 70 6.2E+10 7.5E-14 RUN 3 9 13 1.4E+10 6.2E-14 RUN 5 8 17 2.2E+10 5.5E-14 Total 38 68 106 1.0E+11 7.1E-14 Out of 6 runs, only 4 runs are analyzed for SEU : RUN # 1, 2, 3 and 5. RUN 4 was operated on 320 MHz clock frequency by mistake. In RUN 6, 32 bits were shifted at a time, which made the analyzing very difficult. RUN 2 is the longest run (35 minutes).

SEL test-setup for MPW1 Vdd DSP (1.2V) Vdd (3.3V) Vdd analog (1.2V) Monitoring currents on analog and digital supply VDDA 1.2V: Preamp & ADC VDD 3.3V(2.7V): I/O pad for SAMPA, Output drivers, regulators VDD 1.2V: DSP and shift register Vdd DSP (1.2V) Vdd (3.3V) Current monitoring board FPGA-kit to control shiftregister Vdd analog (1.2V) Measuring voltage over 0.1 ohm resistors using INA226 Monitoring currents from HMP2020 power supply (5V, 1.2V).

No SEL was observed during 1st irradiation tests, with 1 No SEL was observed during 1st irradiation tests, with 1.3 hr beam time and fluence of 1.7e11 p/cm2 σSEL < 6e-12 cm2 Assuming HEH flux of 3400 /cm2/s and 17000 SAMPAs SEL rate < 2e-4/s (MTB SEL > 1.5 hr) Only 1 chip tested (device-to-device variation, temperature and VDD dependency, tungsten?, grazing angles ?) No TID effect observed until 12 kRad One high current event observed (<2s) Disappeared by itself without intervention SELs are typically persistent