Graphène et BN bientôt inséparables ? "Le BN sera au graphène ce que le SiO2 est au Si, en mieux !" Ou encore : "Si le graphène sert un jour à quelque chose, ce sera grâce au BN !" (P. Dollfus, 13 octobre 2011) Institute for Fundamental Electronics, CNRS, University of Paris-Sud, Orsay, France http://computational-electronics.ief.u-psud.fr/
The best : suspended graphene T = 5 K SiO2 substrate: µmax = 25000 cm2/Vs Suspended: µmax = 230000 cm2/Vs
But,… However, suspended graphene is not suitable for applications Need for insulating substrate Standardly used substrate: SiO2 - Compatible with standard processing facilities - Many problems or limitations (mobility): - surface roughness - scattering by charged surface states and impurities Epitaxial Graphene on SiC - Mobility not better than for G reported on SiO2 - Thickness (number of layers) difficult to control - Poor uniformity - Possibility of bandgap ?? (controversy)
The advantages of h-BN substrates The future of graphene: h-BN substrate Xue, Nature Mat. 2011 Same lattice structure, very small lattice mismatch (1.7%) - Free of dangling bonds and surface charge traps - Smooth surface - EG (BN) = 5.97 eV Giovanetti, PRB 2007 (+ bandgap opening in graphene: 53 meV)
The advantages of h-BN substrates Monolayer: µ = 60000 cm2/Vs (electrons) and Bilayer: µ = 60000 cm2/Vs (electrons) and 80000 cm2/Vs (holes) EG 0
Avoiding mechanical transfer ? Yes ! et al. Et ça marche…
Avoiding mechanical transfer ? Yes h-BN as gate insulator (even double-gate ?)
Graphene / h-BN stacks (other information in Zhao Physica E 43 (2010) 440
Towards graphene/h-BN heterostructures
Graphene/h-BN heterostructures
Graphene/h-BN heterostructures
Future works ? By means of tight-binding description of the full device Graphene transistors with single or double BN gate RTD in in-plane G-BN-G-BN-G structures Alternative to: - nanostructuration of GNRs with different sections - doping to generate barriers