Data Handling Processor v0.1 First Test Results Tomasz Hemperek

DHP01 Overview Technology Interface Internal Blocks IBM 90nm – 9 metal layer 1.2 core / 1.8 IO voltage Interface 32 (4x8) 400 MHz inputs from DCD (HSTL18) LVDS control signals (clock, trigger, sync) CMOS JTAG Hi-speed CML output Internal Blocks Common mode correction Pedestal subtraction (static and dynamic*) Zero suppression (threshold) Channel framing and serialization DCD offset correction Raw data storage up to (2048 rows) Sequencer for switcher Configurable delays Clock generation (PLL) Configurable trigger latency (up to 1024 rows) Slow control (JTAG) ADC & DAC 29/09/2010

Slow control - JTAG Boundary scan Configuration 29/09/2010 EXTEST SAMPLE PRELOAD INTEST Configuration BYPASS IDCODE USERCODE ADC BG CORE_READBACK CORE_REG DAC DACENC GLOBAL_REG MEM_ADDRESS MEM_DATA OFFSET_MEM_ADDR OFFSET_MEM_DATA 29/09/2010

DHP – Signal Rates & Data Flow 29/09/2010

DHP Overview 29/09/2010

DHP Processing Deserializer (1 to 4) Common mode correction Buffering for latency Pedestal correction Hit Pairing Readout Output framing Processing algorithms are very simple in current version and need to be adjusted 29/09/2010

Operating modes MEMORY ACCESS RAW DATA RECORD RAW DATA SEND AQUSITION Allows to access memory block through JTAG interface for pedestal and offset correction. RAW DATA RECORD Storing raw data to memory (support for trigger). RAW DATA SEND Sending through fast output link all memory contents. AQUSITION Normal operation mode where data are going through all processing stages. Support for trigger and latency buffering. TEST Like AQUSITION but new data are not being recorded. 29/09/2010

Common mode Pedestal subtraction 8bit + … + 7bit+8bit = 8bit = 8bit 1 127 7bit+8bit = CM 8bit = 8bit 1 … 127 8bit - 1 … 127 store to memory Pedestal subtraction to output n 8bit - n 8bit = n 8bit 29/09/2010

Hit Pairing Parallel pair search (2 rows at a time) suppressed data 4 5 3 1 2 pairs are send out Output data format (24 bits) column row orientation val 0 val 1 5 bit 10 bit 1 bit 8 bit 29/09/2010

DHP01 - Layout Prototype with 32 input chip 4mm OFFSET MEORIES 2mm HSTL RX RAW DATA MEMORIES OFFSET MEORIES RAW DATA MEMORIES 2mm OUT FIFO MEORY LVDS RX 2xPLL CML TX ANALOG ~5.5mln transistors 29/09/2010

DHP01 – Bump bonding 29/09/2010

DHP01 + DCDB 29/09/2010

Test Setup GPIO SMA/Coax Ethernet Ethernet TCP/IP UDP/IP Xilinx XUPV5-LX110T  GPIO SMA/Coax Ethernet TCP/IP Ethernet UDP/IP 29/09/2010

FPGA System Overview Microprocessor responsible for receiving commands (TCP/IP) and controlling chips Independent high-speed (UDP/IP - close to 1Gbit/s) for data 29/09/2010

Simple Application 29/09/2010

Testing till now Working: LVDS Input HSTL like Input (from DCD) Slow control (JTAG) Memories read/write CML Hi-speed link (tested up to 1.555 GHz) data transition Input readout Patter generator DAC Bend Gap To Do: Processing (different configurations) DCD communication and synchronization More High Speed testing 29/09/2010

Power Measurement conditions: Current consumption: 1.2 V, 400MHz (100MHz Core) Current consumption: CML TX - ~25 mA 2xPLL - ~5mA digital core - ~60mA 29/09/2010

PLL and CML 1.5552 GHz – data transmission (random 8b10b) WB + ~5 cm PCB + SMA +~40cm coaxial cable + SMA 100 ps/div 100 mV/div 29/09/2010

Problems till now Looks like CMOS output pads can work till ~100MHz (200MHz when bump bonded?) so unable to test with DCD at 400 MHz Configuration of one PLL output (slow one) not fully accusable (simple bug known from submission) there is a workaround Wrong input data format 29/09/2010

Timeline Finish test setup to be ready for hi-speed data accusation Prepare setup with DCDB Radiation tests DHP 0.2: still half size add custom I/O and bias Redesign serializer to final version Need to develop “final” processing algorithm 29/09/2010

Thank to Bonn: Barcelona: Albert Comerma Angel Dieguez Lluıs Freixes Hans Krüger Andre Kruth Mikhail Lemarenko and others Barcelona: Albert Comerma Angel Dieguez Lluıs Freixes Eva Vilella 29/09/2010

Extra slides 29/09/2010

Performance 29/09/2010

Embedded Development Kit 29/09/2010

Our system 29/09/2010

Transmition 29/09/2010