SPIROC Status : Last release, “SPIROC 2c” Stéphane Callier, Selma Conforti di Lorenzo, Frédéric Dulucq, Gisèle Martin-Chassard, Christophe de La Taille, Ludovic Raux, Nathalie Seguin-Moreau, Damien Thienpont IN2P3/OMEGA-LAL Orsay France raux@lal.in2p3.fr

SPIROC 2c SPIROC 2c submitted in February 27th 2012 and delivery expected in June Pin-to-pin compatibility kept: can be use with the existing HBU Significant improvements: New preamp structure for high gain and low gain (better Signal-to-Noise ratio, less sensitive to coherent noise, Cross-talk between high gain and low gain negligible) Input 8-bit DAC slope uniformity should be reduced TDC (dead time decreased) SPIROC 2c should answer to the SPIROC 2b major bugs: « Pedestal shift » problem « Rate dependency » on preamp « Zero event » bug Problem on delay box for autotrigger Fabricated in AMS SiGe 0.35 µm Submitted in March 2012 Expected in June 2012 Package in T-QFP 208 Chip area : 32 mm² (4.2mm × 7.2mm) Founding : EUDET mercredi 6 juin 2018 Ludovic Raux – SPIROC Status – Calice Meeting, Shinshu University, Matsumoto

New preamp structure used in SPIROC 2c Reminder: Submission in May 2011 of a “Building block” to test and to validate a new preamplifier structure for SPIROC New preamplifier structure based on NMOS input transistor to be less sensitive to coherent noise Preamplifier gain tunable independently on 8 bits (minimum capacitance 6.25 fF) for high gain and for low gain Reminder: Measurement gives good results Signal to noise ratio slightly improved for charge measurement : SNR~20 (10 in spiroc2c) Negligible cross talk between HG and LG observed No “rate dependency” effect measured with this new preamp “Building block” preamp embedded in SPIROC 2c Possibility to bypass the fast shaper and to switch off it (No fast shaper=> power saved) “Building block”: Submission in May 2011 Delivery in October 2011 IN2P3 Funding mercredi 6 juin 2018 Ludovic Raux – SPIROC Status – Calice Meeting, Shinshu University, Matsumoto

SPIROC 2c: bug fix and improvements « Pedestal shift » issue « Pedestal shift » due to coupling on Vdda_pa Should be reduced in SPIROC 2c Modifications on the TDC To decrease dead time during transition => alternation of a rising and a falling ramp implemented Conservative modification but not completely satisfying solution Anyway, a new TDC has to be re-designed in SPIROC 3 © Oskar Hartbrich @Wuppertal mercredi 6 juin 2018 Ludovic Raux – SPIROC Status – Calice Meeting, Shinshu University, Matsumoto

SPIROC 2c: bug fix and improvements Input dac issue Relatively large slope non- uniformity (around 3%) should be slighly improved (better than 1 % expected) Input DAC relatively fragile and could be destroyed if used without precaution (be careful with HV) SPIROC 2c is equiped with more efficient protected pads Delay box issue Delay box does not work properly when several channel are hit This effect should be fixed in SPIROC 2c Signal injected in channel 8 HG value when other channels are hit Decrease of the converted value when several channel are hit at the same time mercredi 6 juin 2018 Ludovic Raux – SPIROC Status – Calice Meeting, Shinshu University, Matsumoto

SPIROC 2c: bug fix and improvements “zero event” occurs randomly Problem should be resolved in SPIROC 2c No digital part change to be conservative but only a D-flip-flop, a gate on ADC discri and delays on control signals mercredi 6 juin 2018 Ludovic Raux – SPIROC Status – Calice Meeting, Shinshu University, Matsumoto

« Roc » chips submission plan for 2012-2013 1st submission (March 2012): SPIROC 2c (2nd generation chip) NMOS Voltage preamp: already integrated in a “building block” SC: old one (No I2C) Pin to pin compatible with spiroc2b so noise measurements can be performed at the system level using the existing HBUs Die size: 32 mm2 => MPW run 32 k€ (CALICE/EUDET funding) 2nd submission (June 2012): HARDROC 3 (3rd generation) « Simple » chip compared to the future Spiroc3 No major modifications in the analog part New integrated features: I2C protocol, independent channels, circular memory, one RAM/channel, new Bandgap, temperature sensor (Vbe), probe register, etc. HR3 won’t be pin to pin compatible with HR2 and probably in a different package: TQFP208 instead of TQFP 160 (same size and thickness) New 1 m2 RPC chamber to be built to test HR3 at the system level Die size should be ~30 mm2 => 30 k€ + 5K test setup (AIDA funding) 3rd submission (March 2013) SPIROC 3 (3rd generation) « Complex chip » , many parts still to be tested on test bench and at the system level I2C protocol, independent channels but also SPIROC2c Preamp, new TDC , new SCA, etc. Hardroc3 and Spiroc2c test feedback necessary before submitting Spiroc3 Digital part : layout completed Size should be ~40 mm2 => 40 k€ + 5 K test setup (AIDA funding) Submitted February 27th mercredi 6 juin 2018 Ludovic Raux – SPIROC Status – Calice Meeting, Shinshu University, Matsumoto

Summary SPIROC 2c submitted on February 27th. Delivery expected in June Should fix major SPIROC 2b bugs (« Pedestal shift » problem, Delay box problem when several channel are hit, Rate dependency on preamp, « Zero events », etc.) And provides improvements (new preamp, input DAC slope uniformity better, etc.) SPIROC 2c is pin-to-pin compatible Next chip to be submitted will be Hardroc 3 (3rd generation of “ROC” chip saga ) SPIROC 3 submission should be in 2013 after Hardroc 3 and Spiroc 2c feedback mercredi 6 juin 2018 Ludovic Raux – SPIROC Status – Calice Meeting, Shinshu University, Matsumoto

Backup slides mercredi 6 juin 2018 Ludovic Raux – SPIROC Status – Calice Meeting, Shinshu University, Matsumoto

HG Preamplifier + Slow shaper Vmax= 46 mV/pe Noise RMS = 2,3mV Analogue signals measurement on the « Building block » Out_SSH_LG 100 pe (16 pC) ; Cf = 200fF Out_PA_HG 1 pe (160 fC) ; Cf = 200fF HG Preamplifier: Gain = 32mV/pe Noise RMS = 1mV SNR ~ 32 Out_SSH_HG 1 pe (160 fC) ; Cf = 200fF HG Preamplifier + Slow shaper Vmax= 46 mV/pe Noise RMS = 2,3mV SNR ~ 20 (Reminder: in SPIROC SNR~10) Other important remarks: No rate effect observed Negligible cross-talk (<1%) mercredi 6 juin 2018 Ludovic Raux – SPIROC Status – Calice Meeting, Shinshu University, Matsumoto

Charge measurement linearity on the building block SSH_HG_Cf=200fF(PA_gain=100) Dynamic: up to 5pC (~ 30pe) SSH_HG_Cf=1pF(PA_gain=20) Dynamic: up to 16pC (~100pe) SSH_LG_Cf=200fF(PA_gain=5) Dynamic: up to 80pC (~500pe) SSH_LG_Cf=1pF(PA_gain=1) Dynamic: up to 300pC (~1875pe) mercredi 6 juin 2018 Ludovic Raux – SPIROC Status – Calice Meeting, Shinshu University, Matsumoto

50% trigger efficiency charge vs threshold (Volts) Trigger efficiency with no fast shaper Trigger capability is down to 1/2pe (~ 80 fC) (Reminder: Trigger efficiency is down to 1/3 pe in SPIROC) The expected 5σ (~ 30 fC) cannot be reached due to a internal coupling via the substrate This coupling is understood and could be easily corrected in the future 50% trigger efficiency charge vs threshold (Volts) S-curves for different injected charges (Trigger efficiency vs threshold (DAC units) 1pe (160 fC) mercredi 6 juin 2018 Ludovic Raux – SPIROC Status – Calice Meeting, Shinshu University, Matsumoto

Preamplifier linearity vs Cf Preamplifier gain tunable independently on 8 bits (minimum capacitance 6.25 fF) 1/Vout vs Cf Nice linearity observed => possibility to adjust the gain channel by channel for HG and LG mercredi 6 juin 2018 Ludovic Raux – SPIROC Status – Calice Meeting, Shinshu University, Matsumoto

Our plans for 2012-2013 : SPIROC 2c New Chip “SPIROC 2c” submission expected in February 2012 Pin-to-pin compatible with “SPIROC 2b” Intermediate chip before SPIROC 3 to validate number of points 1 major improvement: Preamplifier: 3 options : Corrected SPIROC 1 and 2 preamplifier (“Rate dependency”, HG/LG cross-talk) New preamp tested in “building block” Other minor modifications, corrections or improvements Bandgap, delay box, latch on auto-gain discriminator, 4-bit DAC, etc. mercredi 6 juin 2018 Ludovic Raux – SPIROC Status – Calice Meeting, Shinshu University, Matsumoto

Our plans for 2012-2013: SPIROC 3 New Chip “SPIROC 3” submission expected in 2012 or in 2013 depending on the submission of a “SPIROC 2c” version AIDA funding 5 major improvements: Preamplifier: 3 options : Corrected SPIROC 1 and 2 preamplifier (“Rate dependency”, HG/LG cross-talk) New preamp tested in “building block” “Klaus 2” preamplifier New SCA management => real “zero suppress” Channel managed independently -> Implied new digital part (see Frédéric’ talk) SCA Depth will be reduced (from 16 to 8) New TDC => avoid dead time Already existed and tested in PARISROC 2 Slow control by I2C: Developed in collaboration with IPNL Possibility to have a “circular memory mode” Other minor modifications, corrections or improvements Bandgap, delay box, latch on auto-gain discriminator, 4-bit DAC, Slow control cells, etc. mercredi 6 juin 2018 Ludovic Raux – SPIROC Status – Calice Meeting, Shinshu University, Matsumoto

EASIROC (ex-SPIROC 0) EASIROC1a -> ”light” version of SPIROC conservative version of EASIROC EASIROC/SPIROC x bugs corrected Corrected « rate dependency » Switches for Cp capacitances removed Cp=1pF for HG Cp=3pF for LG Corrected cross-talk HG/LG Default slow control setup extended Right value for bias resistances implemented (ibm_pa_lg, ibmin_pa) Submitted on the 2th September 2011 Delivered in December 2011 Validates the correction of the two major problems on the preamps (« rate dependency » and cross-talk HG/LG) mercredi 6 juin 2018 Ludovic Raux – SPIROC Status – Calice Meeting, Shinshu University, Matsumoto