Next Generation Full-chip Circuit Simulation and Analysis December 2002

© Copyright 2002 Nassda Corporation Who is Nassda? We are a fast-growing provider of full-chip circuit verification and analysis software for complex nanometer ICs. © Copyright 2002 Nassda Corporation

Strong Business Performance Over 150 customers 18 of top 20 semiconductor companies rely on Nassda Enabling tapeout success for our customers 2nd fastest growing EDA company in 2001† No. 4 IPO across all industries in 2001 †Dataquest © Copyright 2002 Nassda Corporation

Customer Satisfaction Top technical team from industry and academia committed to customer success No. 1 in Repurchase loyalty Would buy from vendor again No. 2 in Referral potential Would recommend vendor to a colleague No. 3 in Customer satisfaction Source: CMP 2002 EDA Study for all companies © Copyright 2002 Nassda Corporation

Nassda Verification & Analysis Space System Design Synthesis & Circuit Design Pre-Layout Verification HSIM HSIM HSIM Physical Design Nanometer Effects Post-Layout Verification & Analysis HSIM HSIM CRITIC HSIM LEXSIM LEXSIM Tapeout to Manufacture High Perf. ASIC COT Analog & Mixed-Signal SoC Memory © Copyright 2002 Nassda Corporation

Rapid Growth for Nanometer-Scale ICs New challenges Bigger circuit size Parasitic effects (interconnect delay, noise, IR drop, ground bounce, electromigration) Nassda products analyze complex circuits with detailed parasitic effects Source : Company data, Dataquest Oct. 2002 180nm 130nm or below 10 20 30 40 50 60 70 80 90 100 1999 2000 2001 2002E 2003E 2004E © Copyright 2002 Nassda Corporation

A Mixed-Signal IC Example How to design and verify a nanometer mixed-signal IC with several tens of million transistors ? MPEG-4 decoder with audio & video processing, PLL, multiplexer, peripheral I/F & on-chip DRAM © Copyright 2002 Nassda Corporation

Nassda’s HSIM Solution Nassda meets the verification challenge with full-chip circuit simulation and analysis High capacity (> 1 billion transistors) High speed with accuracy Analog, mixed-signal and memory Analysis focus Timing Power Parasitic effects Signal integrity © Copyright 2002 Nassda Corporation

Circuit Simulation Technology Evolution 1st Generation (SPICE) 2nd Generation (Fast SPICE) Next Generation (HSIM) Memory Usage Memory Usage Memory Usage Memory Usage Memory Usage Memory Usage 100M 1G Bytes Bytes Bytes 100K elements 2M elements 512M 512M Bytes Bytes 300M elements Circuit Size Circuit Size Circuit Size Circuit Size Circuit Size Circuit Size CPU Time CPU Time CPU Time CPU Time CPU Time CPU Time 100 100 hrs hrs 20 hrs 20 hrs 100K elements 2M elements 2 hrs 2 hrs 300M elements Circuit Size Circuit Size Circuit Size Circuit Size Circuit Size Circuit Size © Copyright 2002 Nassda Corporation

© Copyright 2002 Nassda Corporation Nassda’s Technology Hierarchical circuit database Hierarchical simulation engine Advanced analog & mixed-signal algorithms Efficient nanometer effects solver Very latest MOS, Bipolar, SOI models Innovative parasitic reduction algorithms © Copyright 2002 Nassda Corporation

© Copyright 2002 Nassda Corporation HSIM Simulation Flow Device Models Spice Netlists VCD Stimulus HSIM Run Log Measure Results Power Check Timing © Copyright 2002 Nassda Corporation

HSIM Capacity & Performance Examples Circuit Type (#MOS, #R,#C,#L) Total Elements Memory Usage CPU Time (hrs) Memory A (159M, 159M, 155M,0) 473M 775MB 1.65 Memory B (3.1M, 5.4M, 4.5M, 88) 13M 195MB 0.69 D/A (9K,65K,47K,0) 121K 42MB 1.11 PLL (2K, 8K, 23K, 0) 51K 15MB 0.21 Analog (119K, 175K, 232K,0) 525K 111MB 0.37 HSIM efficiently analyzes a wide-range of designs © Copyright 2002 Nassda Corporation

© Copyright 2002 Nassda Corporation Mitsubishi 512 Mb DRAM Netlist with over 2 billion elements Simulate 4 Rd / Wr cycles in 6 hours on 32-bit workstation Largest real circuit ever simulated “HSIM has demonstrated many times that it has the speed, accuracy, and capacity for our most sophisticated and complex memory designs. Because HSIM has these unique capabilities, we are able to simulate an entire 512Mb DRAM at the transistor-level with all memory cells in place. This results in Mitsubishi delivering even higher-quality designs with better yield to its customers.” Hisaharu Miwa Manager of EDA Engineering Mitsubishi Electric © Copyright 2002 Nassda Corporation

Pre-Layout Speed Benchmarks Vendor A Runtime HSIM Not possible, exceed capacity Not possible, couldn’t complete Video Chip Network Proc. 1 Network Proc. 2 PLL Mixed Signal MOS: 1.1M 50M 1.8K 300K © Copyright 2002 Nassda Corporation

Post-Layout Speed Benchmarks Vendor B Did not finish after 14 days Vendor A Runtime HSIM Not possible, exceed capacity A/D D/A PLL DRAM 1 DRAM 2 SRAM MOS: 10k 5K 1.5K 120K 150K 200K R: 50k 30K 10K 250K 25K 700K C: 200k 7K 100K 20K © Copyright 2002 Nassda Corporation

Mixed-Signal Success

Success at Silicon Access Networks 20Gbps iFlow Chipset 0.13u TSMC analog/mixed signal designs GHz Ser/Des plus many analog blocks (e.g. PLLs) and megabytes of memory Performance and time-to-market critical HSIM-based verification methodology allowed Silicon Access to… Perform critical analog simulations - PLL power up, synchronization operations, and jitter, and SerDes clock recovery Reduce standby power through leakage checks Have a post-layout timing simulator for all circuits © Copyright 2002 Nassda Corporation

Success at Accelerant Networks 10Gbps Network Transceiver 130K-transistor analog/mixed signal design, .25u TSMC Many Analog Blocks (PLL, DLL, A/D, etc.) Several Thousand Cycles of simulation required for each block Existing simulation solution would have taken weeks (if it completed at all) HSIM-based verification methodology allowed Accelerant Networks to… Verify critical timing performance (PLL settling, clock skew, etc.) Simulate 8uS of Full Chip performance Verify post-layout extracted RLC Drop a cumbersome mixed-mode approach (Verilog/Spice) © Copyright 2002 Nassda Corporation

Memory and Analog Customer Success "We used HSIM extensively and successfully for performing full chip verification of Saifun's non-volatile memory designs. We got an excellent support starting from the business front, continuing with a very good response time to our questions and finally with on-site support. I would like to thank you at Nassda for helping us with our latest tapeouts. These projects are very important to Saifun's future." Ronen Moldovan CAD Manager Saifun “We are working on some of the largest analog integrated circuits in the world. The HSIM tool has enabled us to perform simulations that were simply not possible with any other simulation tool despite the amount of hardware dedicated to the task. We were also very impressed with your sales staff and support." David Madajian Analog IC Design Manager Raytheon © Copyright 2002 Nassda Corporation

© Copyright 2002 Nassda Corporation HSIM Version 2.0 Power leakage analysis CircuitCheck option New SPICE analyses Cadence Analog Artist integration Latest MOS & bipolar models © Copyright 2002 Nassda Corporation

© Copyright 2002 Nassda Corporation CircuitCheck™ Option Static crosstalk and delay analysis at post-layout stage Dynamic operations checks e.g. Vgs > limit && Vds > value Netlist, model, parameter checks Bad values, connections Interactive traceback What caused this signal to change? Save days to weeks of debug time © Copyright 2002 Nassda Corporation

LEXSIM: Full-chip Verification of Power-Net IR Drop

Why Power Net IR Drop Analysis? LVS-clean doesn’t mean complete, correct design Undersized power net structures Missing via, via array, or strapping Finding excessive IR drop not sufficient Determining true performance is critical Delta path delay (%) Post-layout Determine influence of IR drop If you have Fine-line process Low VDD system Probable design failure 10% 20% 30% 40% 1.0V 1.5V 1.8V 2.0V 2.5V 3.0V 3.3V 1.2V 0.25µ 0.13µ IR drop induced change in path delay (%) © Copyright 2002 Nassda Corporation

LEXSIM Post-Layout Tool Full-chip analysis Power net effects IR drop, and influence on design timing Ground bounce (with inductors) Signal net effects Crosstalk-induced noise and delay Glitch power due to coupling capacitors © Copyright 2002 Nassda Corporation

LEXSIM Technology Foundation Production proven simulation engine Power net reduction Efficient disk storage (save/restore) Parasitic annotation to pre-layout Signal nets (ground and coupling cap) Power nets Enables high-speed, high-capacity simulation © Copyright 2002 Nassda Corporation

LEXSIM Benchmark Results © Copyright 2002 Nassda Corporation

LEXSIM Success at Matsushita “Being able to more accurately predict the behavior of our large embedded memory designs requires the inclusion of the effect of IR drops in the power networks. With smaller nanometer geometries and finer metallization, in combination with the higher currents at lower VDDs, we see the need for detailed power-net analysis to prevent possible dynamic IR drop caused design failures. LEXSIM has demonstrated the ability to simulate our full-chip at the post-layout stage including both signal-net and power-net parasitics. We expect to see reduced design turns and faster time-to-volume by using LEXSIM.” Hiroyuki Tsujikawa, Manager, Matsushita’s EDA Technology Development Group © Copyright 2002 Nassda Corporation

CRITIC: Critical Timing Analyzer for Digital ICs

Nanometer Analysis for Digital ICs Critical timing analyzer for post-layout verification of the clock networks and critical paths in cell-based designs Augments gate-level static timing analysis For aggressive designs >300 MHz or in 130nm Automated analysis increases confidence in final timing signoff Nassda’s circuit simulation technology gives best-in-class performance, precision, capacity © Copyright 2002 Nassda Corporation

© Copyright 2002 Nassda Corporation General CRITIC Flow Current flow RTL Design RTL-to-GDSII environment Synthesis, P&R Cell library Verilog netlist Extraction DSPF or SPEF CRITIC Parasitics clock net simulation clock delay report Gate-level STA Critical Paths SDF critical path simulation path delay report © Copyright 2002 Nassda Corporation

Example Critical Path Analysis Result 10-30% difference compared to static timing analysis means possible chip failure CRITIC identifies all cell & path segments contributing to error © Copyright 2002 Nassda Corporation

Enabling Nanometer Silicon Success For more information on why over 150 companies rely on Nassda for verification and analysis of their complex analog, mixed signal, memory, system-on-chip and high performance digital designs, please contact: Nassda Corporation 2975 Scott Blvd., Suite 110 Santa Clara, CA 95054 408-562-9168 Info@nassda.com www.nassda.com © Copyright 2002 Nassda Corporation