Analysis on Performance Controllability under Process Variability: A Step Towards Grid-Based Analog Circuit Optimizers Seobin Jung, Sangho Youn, Jaeha Kim Mixed-Signal IC and System Group Seoul National University, Korea July/2011

Status of Analog Circuit Optimization Absence of systematic design flow Most analog circuit designers do not use the optimizer One of reasons is long execution time Finding a solution in a continuous, high-dimensional design space Most optimizers employ numerical techniques (e.g., simulated annealing, convex optimization) Challenge Process variability and device uncertainty worsen the situation by accompanying complex physical phenomena Let’s start with checking current status of analog circuit optimization briefly. Compared to digital circuit design, analog circuit design employs relatively weak design flow. For optimization case, although many researchers have developed analog circuit optimizers for decades, unfortunately, most designers do not use them. There might be several reasons for this, and one of them is the long execution time. Unlike designing a digital circuit, designing an analog circuit involves exploring a continuous design space, and often, the space is high dimensional. For this reason, most of analog circuit synthesis tools employ numerical techniques like simulated annealing and convex optimization. However, for these optimizers, there is one more challenge. As technology is more scaled, the effect of process variability and device uncertainty is being emphasized. This is not a good news, because for simulation-based optimizers, it means optimizer would require heavier simulation to cope with complex physical phenomena, and for equation-based optimizers, it would be quite difficult to describe them all mathematically.

Common Issues with Continuous Optimizers Continuous optimizers can waste computational efforts When refining the solution to the irrelevant precision When making unsuccessful escape attempts to search for other local optimas The optimum is 32.4974384! Now the optimization problem seems really tough, but if we think about what optimizers really do, we can take a different approach. So now let's see the common problem of optimizers for exploring the continuous design space. They can waste computational efforts with doing unwanted jobs. I’ll address this issue with an example. This graph is about a 5-stage simple ring oscillator. The x-axis is the design parameter Wp of the inverter, and the y-axis is the oscillation period. I’ve fixed the width of NMOS to 30 lambda, and tried to find the optimal Wp which makes the oscillator to have the minimum period. If I let the continuous optimizer to do this job, it’ll response that Wp should be 32.4974…., but I’ll just use 32, since that’s enough. When the optimizer reaches the near-optimum, it calculates the neighbor of optimum exhaustively to refine the solution. And there is one more problem. The optimizer needs to cope with the surface roughness. Although I’ve got this clear roughness by lowering the precision of circuit simulator, the roughness exists indeed. As a result, the extra effort is needed for the optimizer not to be stuck in local optima. Thanks. I’ll just use 32; that’s close enough

Leveraging Process Variability In presence of variation and uncertainty, designers have limited control over the precision in performance metrics Two design points must be sufficiently different to be distinguished by their performance metrics

How Much Different Should They Be? Shannon’s channel capacity theorem tells us how much signal swing (DX) is required to convey N-bit of information in presence of noise For sending 1-bit of information (distinguishing two points):

Minimum Design Change Required (DDmin) We can consider a circuit as an effective channel medium that yields a certain performance with finite precision in response to the design parameter values To tell two design points apart by their performance (P):

DDmin in Ring Oscillator Performance P = oscillation period Design parameter D = Wload Fixed value : Wring = 20λ

DDmin in Differential Amplifier Performance P = DC gain Design Parameter D = W Fixed values : R = 10kΩ, Wtail = 20λ

DDmin in Real Circuit Examples To our surprise, the minimum change required is > 20%! This motivates a coarse grid-based optimization approach With 20% log-scale grid, 1:10 range requires only 13 points!

Potentials for Grid-Based Optimizers Unlike continuous ones, coverage can be defined Avoids evaluating similar design points during local search Knows which space is less explored during global search The optimum is 32 Thanks! It’s reasonable

Challenges for Grid-Based Optimizers Defining the discrete grid for the design space For Cartesian grids, the number of points in the space grows exponentially with the dimension N Navigating the grid for local search Compare the current design with the neighbors and update But the number of neighbor points grows exponentially Making comparisons between two design points Must be done in statistically sense Involves costly Monte-Carlo simulations

Conclusion In presence of process variability and uncertainty, grid-based analog circuit optimizer may be a viable approach The continuous design space can be transformed into the discrete design space For a few common circuits, the minimum grid spacing required was quite coarse (~20%)