ChapTer FiVE FIELD EFFECT TRANSISTORS (FETs) .…Electronic I.… ..DMT 121/3.. ChapTer FiVE FIELD EFFECT TRANSISTORS (FETs)

THE JFET BJT – current controlled, IC is direct function of IB Fig. 6.1 (a) Current-controlled and (b) voltage-controlled amplifiers. FIGURE 7-1 A representation of the basic structure of the two types of JFET. BJT – current controlled, IC is direct function of IB FET – voltage controlled, ID is a direct function of the voltage VGS applied to the input circuit.

FET FETs (Field-Effect Transistors) are much like BJTs (Bipolar Junction Transistors). Similarities: Amplifiers Switching devices Impedance matching circuits Differences: FETs are voltage controlled devices whereas BJTs are current controlled devices. FETs also have a higher input impedance, but BJTs have higher gains. FETs are less sensitive to temperature variations and because of there construction they are more easily integrated on ICs. FETs are also generally more static sensitive than BJTs. FETs are usually smaller than BJTs and particularly useful for IC chips.

FET Types JFET–– Junction Field-Effect Transistor MOSFET –– Metal-Oxide Field-Effect Transistor D-MOSFET –– Depletion MOSFET E-MOSFET –– Enhancement MOSFET

Basic Operation of a JFET JFET operation can be compared to a water spigot. The source of water pressure is the accumulation of electrons at the negative pole of the drain-source voltage. The drain of water is the electron deficiency (or holes) at the positive pole of the applied voltage. The control of flow of water is the gate voltage that controls the width of the n-channel and, therefore, the flow of charges from source to drain.

Basic Operation of JFET

JFET Structures & Symbols JFET Symbols JFET Structures

JFET Characteristics and Parameters, VGS = 0 Let’s first take a look at the effects with a VGS of 0V. ID increases proportionally with increases of VDD (VDS increases as VDD is increased). This is called the ohmic region (point A to B). In this area (ohmic region) the channel resistance is essentially constant because of the depletion region is not large enough to have sufficient effect  VDS and ID are related by Ohm’s law In JFET, IG = 0  an important characteristic for JFET

JFET Characteristics and Parameters, VGS = 0 At point B the ID cease to increase regardless of VDD increases. This called pinch-off voltage. As VDD increase from point B to point C, the reverse-bias voltage from gate to drain (VGD) produces a depletion region large enough to offset the increase in VDS, thus keeping ID relatively constant.

JFET Characteristics and Parameters, VGS = 0 Continue increase in VDS above the pinch-off voltage produces an almost constant drain current  this drain current is IDSS (drain to source current with gate shorted). Breakdown occurs at point C when ID begins to increase very rapidly with any further increase in VDS. It can result irreversible damage to the device, so JFETs are always operated below breakdown and within the constant-current area (between points B and C on the graph)

JFET action for VGS = 0V

JFET Characteristics and Parameters, VGS < 0 As VGS is set to increasingly more negative by adjusting VGG. A family of drain characteristic curves is produced as shown in (b). Notice that ID decrease as the magnitude of VGS is increased to larger negative  causing the pinch-off is lowered as well (Boystead – lower in parabolic manner)

JFET Characteristics and Parameters, VGS < 0; VGS (off) As VGS becomes more negative: The JFET experiences pinch-off at a lower voltage (Vp). ID decreases (ID < IDSS) even though VDS is increased. Eventually ID reaches 0A. VGS at this point is called Vp or VGS(off) ( VGS (off) = VP) Take note at Ohmic & Saturation Region FLOYD  VGS (off) = - VP ; reverse polarity Also note that at high levels of VDS the JFET reaches a breakdown situation. ID increases uncontrollably if VDS > VDSmax.

JFET Characteristics and Parameters, VGS < 0; VGS (off) For cutoff voltage (VG(off)). The field (in white) grows such that it allows practically no current to flow through.

JFET Transfer Characteristics The transfer characteristic of input-to-output is not as straightforward in a JFET as it is in a BJT. In a BJT,  indicates the relationship between IB (input) and IC (output). IC = IB In a JFET, the relationship of VGS (input) and ID (output) is a little more complicated:

JFET Transfer Curve When VGS = 0; ID = IDSS This graph shows the value of ID for a given value of VGS. When VGS = 0; ID = IDSS When VGS = VGS (off) = VP; ID = 0 mA

Plotting the JFET Transfer Curve Using IDSS and Vp (VGS(off)) values found in a specification sheet, the transfer curve can be plotted according to these three steps: Solving for VGS = 0V ID = IDSS Step 1 Solving for VGS = Vp (VGS(off)) ID = 0A Step 2 Solving for VGS = 0V to Vp Step 3

JFET Biasing JFET ID = IS IG  0 A BJT IC = IB IC  IE VBE  0.7 V Just as we learned that the bi-polar junction transistor must be biased for proper operation, the JFET too must be biased for operation. Let’s look at some of the methods for biasing JFETs. In most cases the ideal Q-point will be the middle of the transfer characteristic curve which is about half of the IDSS. JFET ID = IS IG  0 A BJT IC = IB IC  IE VBE  0.7 V

JFET Biasing, Fixed- Bias Configuration Fig. 7.1 Fixed-bias configuration. Fig. 7.2 Network for dc analysis. IG = 0 so VRG = IGRG = (0 A)RG = 0 then RG can be removed from the circuit. RG only need in ac analysis through the input Vi - VGG – VGS = 0 VGS = - VGG

JFET Biasing, Fixed- Bias Configuration Drain-to-source voltage can be determined by applying Kirchoff’s voltage law VDS + IDRD –VDD = 0 VDS = VDD – IDRD Source voltage to ground; VS = 0 Drain-to-source voltage can also be determined through; VDS = VD – VS but VS = 0 then VDS = VD Fig. 7.5 Measuring the quiescent values of ID and VGS. Gate-to-source voltage VGS = VG – VS ; since VS = 0 VGS = VG Since the configuration requires two dc supply, its use is limited and not included in the list of common FET configurations.

JFET Biasing, Self- Bias Configuration Most common type of JFET bias. Eliminates the need for two dc supplies. The controlling gate-to-source is determined by the voltage across a resistor RS. For analysis, resistor RG replaced by a short circuit equivalent since IG = 0 A. Fig. 7.8 JFET self-bias configuration. Fig. 7.9 DC analysis of the self-bias configuration.

JFET Biasing, Self- Bias Configuration Voltage drop across source resistor, RS VRS = ISRS; since IS = ID then VRS = IDRS For indicated closed loop in the Figure 7.9 -VGS – VRS = 0 VGS = - VRS VGS = -IDRS Drain current, ID: Fig. 7.9 DC analysis of the self-bias configuration.

JFET Biasing, Self- Bias Configuration Voltage between drain-to-source, VDS VDD – IDRD – VDS – ISRS = 0 Since IS = ID VDD – IDRD – VDS – IDRS = 0 VDS = VDD – ID(RD + RS) OR VDS = VD – VS VS = ISRS and VD = VDD – IDRD Voltage between gate-to-source, VGS VGS = VG – VS; Since VG = 0 VGS = -VS and VS = ISRS Then VGS = - ISRS Fig. 7.9 DC analysis of the self-bias configuration.

JFET Biasing, Self- Bias Configuration The value of RS needed to establish the computed VGS can be determined by the previously discussed relationship below. RS = | VGS/ID | The value of RD needed can be determined by taking half of VDD and dividing it by ID. RD = (VDD/2)/ID Fig. 7-16a n channel JFET Fig 7-12 n channel curve

JFET Biasing, Self- Bias Configuration Remember the purpose of biasing is to set a point of operation (Q-point). In a self-biasing type JFET circuit the Q-point is determined by the given parameters of the JFET itself and values of RS and RD. Setting it at midpoint on the drain curve is most common. One thing not mentioned in the discussion was RG. It’s value is arbitrary but it should be large enough to keep the input resistance high. Fig. 7-16a n channel JFET

JFET Biasing, Voltage-Divider Configuration The basic construction exactly the same with BJT, but the dc analysis quite different with IG = 0 for FET The voltage at source, VS must be more positive than the voltage at the gate, VG in order to keep gate-source junction reverse-biased. Gate-to-source analysis VS = IDRS Gate-to-source voltage; VGS = VG – VS And source voltage is VS = VG – VGS The drain current can be expressed as

JFET Biasing, Voltage-Divider Configuration Drain-to-source analysis VDS = VDD – ID(RD + RS) VD = VDD – IDRD VS = IDRS

MOSFET – metal oxide semiconductor field-effect transistor The MOSFET MOSFET – metal oxide semiconductor field-effect transistor Two basic types of MOSFET Depletion – MOSFET Enhancement - MOSFET

The MOSFET The metal oxide semiconductor field effect transistor (MOSFET) is the second category of FETs. The chief difference is that there no actual pn junction as the p and n materials are insulated from each other. MOSFETs are static sensitive devices and must be handled by appropriate means. There are depletion MOSFETs (D-MOSFET) and enhancement MOSFETs (E-MOSFET). Note the difference in construction. The E-MOSFET has no structural channel. Fig 7-29 D-MOSFET construction Fig 7-32 E-MOSFET construction

The MOSFET The D-MOSFET can be operated in depletion or enhancement modes. To be operated in depletion mode the gate is made more negative effectively narrowing the channel or depleting the channel of electrons. Fig 7-30a depletion mode Fig 7-31 DMOSFET schem. symbols

The MOSFET To be operated in the enhancement mode the gate is made more positive, attracting more electrons into the channel for better current flow. Remember we are using n channel MOSFETs for discussion purposes. For p channel MOSFETs, polarities would change. Fig 7-30b enhancement mode

The MOSFET The E-MOSFET or enhancement MOSFET can operate in only the enhancement mode. With a positive voltage on the gate the p substrate is made more conductive. Fig 7-32 n channel EMOSFET Fig 7-33 EMOSFET schem. symbols