Fast retrigger path What threshold level we need for the fast trigger path?

Slides:



Advertisements
Similar presentations
Chapter 10 Analog Integrated Circuits The 741 OP-AMP Introduction.
Advertisements

» When you have completed this module you will know, what components do, what they physically look like and how they are represented in a circuit diagram.
N. Voumard, AB-BT-EC LBDS Audit, CERN LBDS Trigger Signal Distribution Trigger Synchronization Unit (TSU) Trigger Fan Out (TFO) Power Trigger Unit.
ECE 4501 Lecture 11: Rectifiers, Switches and P ower Supplies.
ECD 442 Power Electronics1 Power MOSFETs Two Types –Depletion Type Channel region is already diffused between the Drain and Source Deplete, or “pinch-off”
Spark Chamber I Spark Chamber in Vienna Museum of Technology Using Sparks to Image Particle Tracks.
Transistors in Parallel. Why connect transistors in parallel? Connect in parallel to handle high currents Need to be closely matched for equal current.
1 MKBH Erratic Jan Uythoven On behalf of the ABT team (Viliam, Nicolas M., Etienne, Laurent, Francesco etc…..) MPP meeting 8/5/2015.
Digital CMOS Logic Circuits
Astable multivibrators I
The 555 as an Astable Multivibrator. Inside look at a 555 Integrated Circuit Timer.
Zero Crossing Detector
Higher order effects Channel Length Modulation Body Effect Leakage current.
1 LBDS Testing Before Operation Jan Uythoven (AB/BT) Based on the work of many people in the KSL, EC and TL sections.
LBDS Power Triggering Etienne CARLIER & Jean-Louis BRETIN AB/BT/EC.
POWER AMPLIFIER Class B Class AB Class C.
CHAPTER 8 MOSFETS.
ILC Hybrid MOSFET/Driver Module Update T. Tang, C. Burkhart September 29, 2011.
1. Digital cmos.2 10/15 Figure 10.1 Digital IC technologies and logic-circuit families. Digital IC Technologies CMOS & Pass Transistor Logic dominate.
Linear Power Supplies, Switched Mode Power Supply
1 13. Pulsed waveforms and Timing Circuit Design 13.1Op. Amp. Pulse GeneratorsOp. Amp. Pulse Generators timer IC Oscillator555 timer IC Oscillator.
TRIGGER DELAY 100µs. G. Gräwer AB/BT/ECLBDS Trigger Delay2 The trigger delay is a back-up system that generates an asynchronous dump trigger for MKD and.
The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering ECE122 – 30 Lab 2: NAND gate.
Monostable Multivibrator
Chapter 13 Small-Signal Modeling and Linear Amplification
Rectifiers, Switches and Power Supplies
Logic Families.
Clock Signals: 555 Timer 555 Timer Digital Electronics TM
Visit for more Learning Resources
Voltage Doublers A voltage doubler provides an output that is twice its peak input voltage.
To Design and Implement Monostable Multivibrator Circuit Using IC555
EI205 Lecture 8 Dianguang Ma Fall 2008.
AIDA design review 12 May 2008 Davide Braga Steve Thomas
Proposition of MKD & MKBH modification with the goal to reduce maximum voltage (and risk of erratic) Viliam Senaj, 05/05/2017.
Lecture 21 OUTLINE The MOSFET (cont’d) P-channel MOSFET
LHC Beam Dumping System Reliability Run Summary
MKD/MKB Review Meeting Scope and Definition
Recall Last Lecture The MOSFET has only one current, ID
AC Inlet & AC Input Filter
Electronic Circuits Laboratory EE462G Lab #6
Chapter E –Transistors and H-Bridges
EI205 Lecture 15 Dianguang Ma Fall 2008.
Institute of Technology
Small-Signal Modeling and Linear Amplification
NAND Gate Truth table To implement the design,
BJT transistors.
Sedr42021_0434.jpg Figure 4.34 Conceptual circuit utilized to study the operation of the MOSFET as a small-signal amplifier.
Presented by: Sanjay Pithadia SEM – Industrial Systems, Medical Sector
Digital Computer Electronics TTL
Week 9a OUTLINE MOSFET ID vs. VGS characteristic
Reading: Finish Chapter 17,
Transistors (MOSFETs)
Qualitative Discussion of MOS Transistors
Prof. Hsien-Hsin Sean Lee
MOSFET – Common-Source Amplifier
Lecture 21 OUTLINE The MOSFET (cont’d) P-channel MOSFET
Lecture 21 OUTLINE The MOSFET (cont’d) P-channel MOSFET
Is there anything we can do to keep from going into this state?
Week 9a OUTLINE MOSFET ID vs. VGS characteristic
EENG447 Digital IC Design Dr. Gürtaç Yemişcioğlu.
Lecture 21 OUTLINE The MOSFET (cont’d) P-channel MOSFET
EE115C – Winter 2009 Digital Electronic Circuits
Lecture #17 (cont’d from #16)
MOSFETs AIM: To understand how MOSFETs can be used as transducer drivers PRIOR KNOWLEDGE: Output transducers, Current in circuits, Calculating resistor.
Mark Bristow CENBD 452 Fall 2002
Recall Last Lecture The MOSFET has only one current, ID
Analysis of Single Stage Amplifiers
Lecture #16 OUTLINE MOSFET ID vs. VGS characteristic
Status of the retriggering boxes and measurements
Chapter 13 Small-Signal Modeling and Linear Amplification
Presentation transcript:

Fast retrigger path What threshold level we need for the fast trigger path?

Simulations - Old transistor Schematic Simulation Trigger path Current schematic To IGBT Retrigger path Fast retrigger path : MOSFET Reference 2N6782 Continuous drain current 3.5A Pulsed drain current 14A Turn-ON Delay Time 15ns VGS(th) 2.0-4.0 V This pulse has the voltage as variable parameter.

Vgsth for old and new Mosfet Mosfet IRF7452 (New schematic) Mosfet 2N6782 (Old schematic) Voltage at the secondary of the pulse transformer Vds of the Mosfet Input voltage = 4.1V Input voltage = 4.2V Input voltage = 6V Input voltage = 6.1V Complementary information : -> Length of the pulse = 6 us for both

Switching time 100ns between the input pulse and the Mosfet switching Trigger path Retrigger path 100ns between the input pulse and the Mosfet switching Indicator Circuit Propagation delays IC4 HEF4072B 55ns IC3 HEF4528B 70ns IC1 HEF4049 25ns T1 2N6782 15ns   Total 165ns

IPOC waveforms Complementary information : -> The values given below must be multiplied by 10 MKD RTRIG.B1 MKB RTRIG.B2 Input signals to the PTM. Very low voltage (between 3V and 4V)

MKBH – data coming from Viliam MKBH: Ch1,2 = Cts1, Cts2; Ch3,4 = retrig OUT a,b left: normal pulse at 7.1 TeV with late discharge of accumulated charge right: big sparking and its coupling to RB output (> 6V peak)

Improvements Change the MOSFET in order to reduce the switching sensibility(Vgs). Replace by another with higher Vgs. IPOC : Increase the voltage level in order to be superior to the value of sparking(>6V) => It will be more judicious to have an important difference between the voltage sparking (>6V) and the threshold. If we have to chose between 7.5V and 10V, 10V will be more careful.