RTOS Scheduling 3 Cyclic scheduling, EDF. Tasks with precedence, Scheduling impact of DMA, cache, interrupts & context switch overhead, Aperiodic Georgio Butazzo, “Predictable scheduling Algorithms and applications”, 3rd edition 4/16

Scheduling Approaches Summary Off-line scheduling / analysis (static analysis - static scheduling) All tasks, times, priorities given Time-driven; schedule hardcoded, does not use kernel sched. E.g., Cyclic Executives Inflexible – reliable used  Military, space Fixed priority scheduling (static analysis + dynamic scheduling) All tasks, times and priorities given Priority-driven, dynamic scheduling  run time scheduling Used hard / safety critical systems E.g., RMA/RMS Dynamic priority scheduling ( dynamic priorities) Tasks times may not be known priorities based on current system - dynamic For hard / best effort systems E.g., Earliest Deadline, First (EDF), 4/16

Simple off-line Algorithm Offline, static: Cyclic (a.k.a. Time Line ) Scheduling defence – military – traffic control Time divided into slices. Greatest Common Divisor of Periods  time slice: 25ms for example – minor cycle, min. cycle of repetition = major cycle Butazzo : chapter 4, 4.2 The method consists of dividing the temporal axis into slots of equal length, in which one or more tasks can be allocated for execution, in such a way to respect the frequencies derived from the application requirements. A timer synchronizes the activation of the tasks at the beginning of each time slot. The main advantage of timeline scheduling is its simplicity. The method can be implemented by programming a timer to interrupt with a period equal to the minor cycle and by writing a main program that calls the tasks in the order given in the major cycle, inserting a time synchronization point at the beginning of each minor cycle. Since the task sequence is not decided by a scheduling algorithm in the kernel, but it is triggered by the calls made by the main program, there are no context switches, so the runtime overhead is very low. Moreover, the sequence of tasks in the schedule is always the same, can be easily visualized, and it is not affected by jitter (i.e., task start times and response times are not subject to large variations). In spite of these advantages, timeline scheduling has some problems. For example, it is very fragile during overload conditions. If a task does not terminate at the minor cycle boundary, it can either be continued or aborted. In both cases, however, the system may run into a critical situation. In fact, if the failing task is left in execution, it can cause a domino effect on the other tasks, breaking the entire schedule (timeline break). On the other hand, if the failing task is aborted while updating some shared data, the system may be left in an inconsistent state, jeopardizing the correct system behavior. Another big problem of the timeline scheduling technique is its sensitivity to application changes. If updating a task requires an increase of its computation time or its activation frequency, the entire scheduling sequence may need to be reconstructed from scratch. Considering the previous example, if task B is updated to B’ and the code change is such that CA + CB > 25ms , then task B’ must be split in two or more pieces to be allocated in the available intervals of the timeline. Changing the task frequencies may cause even more radical changes in the schedule. For example, if the frequency of task B changes from 20 Hz to 25 Hz (that is TB changes from 50 to 40 ms), the previous schedule is not valid any more, because the new Minor Cycle is equal to 5 ms and the new Major Cycle is equal to 200 ms. Note that after this change, since the Minor cycle is much shorter than before, all the tasks may need to be split into small pieces to fit in the new time slots. Finally, another limitation of the timeline scheduling is that it is difficult to handle aperiodic activities efficiently without changing the task sequence. The problems outlined above can be solved by using priority-based scheduling algorithms. Example: TA = 25ms, TB = 50ms, TC = 100ms Task A executed every time slot, Task B every two slots, Task C every 4 slots Simple off-line Algorithm 4/16

2nd Cyclic Executive example:fyi Car controller Speed measurement C= 4ms, P = 20ms, D = 20ms ABS control C= 10ms, P = 40ms, D = 40ms Fuel injection C= 40ms, P = 80ms, D = 80ms Other Shortest repeat cycle = 80 ms 4 14 20 24 40 44 54 60 64 76 80 speed ABS fuel1 speed fuel2 speed ABS fuel3 speed fuel4 other 4/16

Cyclic Executive pros & cons Pros: Simple to implement, does not use kernel scheduler, timer interrupt every minor cycle – main calls tasks; No switching OH Pros: Predictable, Good for safety critical app. Con: waste CPU time Con: difficult to modify - add task eg increase task time may exceed minor cycle Con: poor fragile overload handling– eg task does not terminate (Aborted ?) ..domino effect Con: non optimal response time 4/16

RM vs. EDF Rate Monotonic fixed priority / Dynamic scheduling Simpler implementation Predictability for highest priority tasks EDF dynamic priority Full processor utilization Misbehavior during overload conditions 4/16

EDF (Earliest Deadline First) dynamic priority scheduling I no precedence task with shorter deadline has higher priority Executes job with earliest deadline Example T1 (4,1) T2 (5,2) 5 10 15 T3 (7,2) 4/16

EDF Optimal algorithm - if there is a schedule, EDF can schedule it. (4,1) T2 (5,2) 5 10 15 T3 (7,2) 4/16

Scheduling tasks with precedence relations Scheduler {T1, T2} Conventional task set T1 T2 Tasks with precedence constraints 4/16

Scheduling Tasks with Precedence – use DAG - fyi 1 2 3 4 5 6 DAG : task 1 must complete before tasks 2 and 3 start, etc. directed acyclic graph – (DAG) indicates which tasks must complete before other tasks start. 4/16

Example: EDF Scheduling of Tasks with precedence II 1 2 3 4 5 6 C1 = 1 d1 = 2 C3 = 1 d3 = 4 C2 = 1 d2 = 5 C4 = 1 d4 = 3 C5 = 1 d5 = 5 C6 = 1 d6 = 6 Task 3 chosen before 4 because of precedence Next we schedule 2 & 4 has missed deadline (3) Determine schedule feasibility 4/16

EDF not optimal under precedence constraints – but minimizes latencies 1 2 3 4 5 6 C1 = 1 d1 = 2 C3 = 1 d3 = 4 C2 = 1 d2 = 5 C4 = 1 d4 = 3 C5 = 1 d5 = 5 C6 = 1 d6 = 6 EDF Schedule 1 3 2 4 5 6 2 4 6 task 3 chosen at time 1 ; has earlier deadline. Result: task 4 misses its deadline 4/16

Solution: modify EDF task parameters release time & deadlines Modify task parameters to respect precedence constraints Scheduler Tasks with precedence constraints Schedule queue 4/16

Task release time & deadlines changed  EDF Using EDF scheduler, task – release time & deadline modified to respect precedence constraints Rj* ≥ Max (Rj, (Ri* + Ci)) new release time Di* ≥ Min (Di, (Dj* – Cj)) new deadline Ti Tj 4/16

Modifying Release times for EDF Example R1 = 0 R2 = 5 T1 1 T2 2 R4’ = max(R1+C1, R2+C2,R4) R3’ = max(R1 + C1, R3) Initial Task Parameters R3 = 0 Task Ri Ci Di T1 1 5 T2 2 7 T3 T4 10 T5 3 12 R3’ = 1 R4 = 0 T3 2 T4 1 R4’ = 7 T5 3 R5 = 0 R5’ = 8 R5’ = max(R3’+C3, R4’+C4,R5) 4/16

Modifying release times for EDF 1 T2 2 Modified Task Parameters Task Ri Ci Di T1 1 5 T2 2 7 T3 T4 10 T5 8 3 12 R3’ = 1 T3 2 T4 1 R4’ = 7 T5 3 R5’ = 8 4/16

Modifying Deadlines for EDF D2’ = Min( (D4’ – C4), (D3’ – C3), D1) D1 = 5 D2 = 7 D1’ = 3 D2’ = 7 T1 1 T2 2 D2’ = Min( (D4’ – C4), D2) Modified Task Parameters Task Ri Ci Di T1 1 5 T2 2 7 T3 T4 10 T5 8 3 12 D3 = 5 T3 2 D3’ = 5 T4 1 D4 = 10 D4’ = 9 T5 3 D5 = 12 D3’ = Min( (D5 – C5), D3) D4’ = Min( (D5 – C5), D4) 4/16

Modified Deadlines & release times for EDF 1 T2 2 Modified Task Parameters Task Ri Ci Di T1 1 3 T2 5 2 7 T3 T4 9 T5 8 12 T3 2 D3’ = 5 T4 1 D4’ = 9 T5 3 D5 = 12 4/16

Real time systems Predictability Problems _ DMA Direct Memory Access transfer data between device , main memory Problem: I/O device and CPU share same bus  good for performance, but –ve bad for predictability solutions: Cycle stealing DMA steals CPU memory cycle for its data transfer CPU waits until DMA transfer complete Source of non-determinism! Time-slice method memory cycle split in two adjacent time slots One for the CPU One for the DMA More costly, but more predictable! 4/16

Predictability Problems: Cache To obtain high predictability, better to have processors without cache ; sacrifice some performance Source of non-determinism cache miss vs. cache hit  miss penalty writing vs. reading; needs write through  memory 4/16

Predictability Problems: Interrupts One of biggest problem for predictability Typical device driver <enable device interrupt> <wait for interrupt> <transfer data> In OS Interrupts  service routine interrupts served with fixed static priority interrupts have higher priorities than processes, but processes may be higher importance than I/0 operation! delay introduced by interrupts, # interrupts occur during a task? unpredicatble 4/16

Predictability Problems: Interrupts Solutions – approaches Disable interrupts, except timer I/O handled by application, polling -ve sacrifice efficienc, busy – wait, cumbersome Interrupts disabled, same as 1; but periodic Kernel routine(s) manages I/O +ve limit bound on service; hides I/O details -ve still has busy-wait, OH due to app kernel communication Enable Interrupts; strip down service to activate a task +ve task scheduled with rest – under kernel control, priorities managed +ve eliminate busy – wait -ve still has some driver unbounded delys 4/16

Handling Interrupts – example T0 - interrupt handler; Highest priority C T T0 (int.) 60 200 T1 10 50 T2 40 250 T0 Missed deadline 60 100 200 T1 T2 50 60 4/16

C T IH 10 200 T1 50 T2 40 150 T3 Handling Interrupts – example solution: interrupt handler  IH & T3 move some code from handler to another task T3 with same rate IH highest priority, may conflict with RM IH 100 150 200 T1 T2 50 60 T3 4/16

Handling Context Switch Overhead Assume Cl = time required to load new task Cs = time required to save current task context (Cl = Cs) Task1 Task 2 Task 3 OH subtracted from budget every period 4/16

Handling Aperiodic Tasks Solutions Immediate service Background scheduling Aperiodic servers 4/16

Aperiodic: Immediate Service Aperiodic request  served as soon as they arrive in system Minimum response times for aperiodic requests But Weak guarantees for periodic tasks Example 4/16

Aperiodic: Background Scheduling Handle soft aperiodic tasks in background behind periodic tasks – in processor free time - after scheduling all periodic tasks Aperiodic tasks  lower priority than periodic tasks Organization: 4/16

Latest Deadline First (LDF) 1973 FYI build schedule backwards. example EDF Schedule C2 = 1 d2 = 5 4 1 3 2 4 5 6 2 C5 = 1 d5 = 5 1 5 C1 = 1 d1 = 2 3 C3 = 1 d3 = 4 6 1 2 4 3 5 6 C6 = 1 d6 = 6 LDF Schedule Used with precedence constrained tasks DAG Directed acyclic graph to analyze EDF – early deadline first – variation of LDF LDF scheduling strategy: build schedule backwards. Given a DAG, choose leaf node with latest deadline to be scheduled last, work backwards. 4/16

Latest Deadline First (LDF) example C4 = 1 d4 = 3 C2 = 1 d2 = 5 4 2 C5 = 1 d5 = 5 1 5 C1 = 1 d1 = 2 3 C3 = 1 d3 = 4 6 C6 = 1 d6 = 6 Build schedule backwards. Given DAG, choose leaf node with latest deadline (6) to be scheduled last - work backwards. Look at 3, 4, 5 next The LDF scheduling strategy builds a schedule backwards. Given a DAG, choose the leaf node with the latest deadline to be scheduled last, and work backwards. 4/16

Latest Deadline First (LDF) C4 = 1 d4 = 3 C2 = 1 d2 = 5 4 2 C5 = 1 d5 = 5 1 5 C1 = 1 d1 = 2 3 C3 = 1 d3 = 4 6 C6 = 1 d6 = 6 5 is next. , look at 3,4 next 4/16

Latest Deadline First (LDF) C4 = 1 d4 = 3 C2 = 1 d2 = 5 4 2 C5 = 1 d5 = 5 1 5 C1 = 1 d1 = 2 3 C3 = 1 d3 = 4 6 C6 = 1 d6 = 6 3 4/16

Latest Deadline First (LDF) C4 = 1 d4 = 3 C2 = 1 d2 = 5 4 2 C5 = 1 d5 = 5 1 5 C1 = 1 d1 = 2 3 C3 = 1 d3 = 4 6 C6 = 1 d6 = 6 4/16

Latest Deadline First (LDF) C4 = 1 d4 = 3 C2 = 1 d2 = 5 4 2 C5 = 1 d5 = 5 1 5 C1 = 1 d1 = 2 3 C3 = 1 d3 = 4 6 C6 = 1 d6 = 6 4/16

Latest Deadline First (LDF) optimal under precedence constraints 4 2 C5 = 1 d5 = 5 1 5 C1 = 1 d1 = 2 3 C3 = 1 d3 = 4 6 C6 = 1 d6 = 6 The LDF schedule - respects all precedence and meets all deadlines. 4/16