DHCAL TECH PROTO READOUT PROPOSAL Calice Meeting, Oct. 13th Michel Bouchel Christophe de La Taille Gisèle Martin Julien Fleury

The context : Technologic R&D A work group to study final ASIC issues LLR, Palaiseau ; IPN, Lyon ; LAL, Orsay In parallel with ECAL ASIC study  Because most issues are the same - Digital backend - Power pulsing Be able to put a techno proto layer in physic proto (just like ECAL)

Our starting point : The detector : RPC Signal Pad Mylar sheet Resistive paint 1.1mm Glass sheet Glass Normal floating glass Resistive paint Graphite or conductive ink Spray or silk screen printing Controlled resistivity (0.1 – 10 MΩ/) Spacer Fishing line RPC is simple and reliable No aging effect has ever been observed for glass RPC Easy to construct, low cost High efficiency and good position resolution perfect for a DHCAL 1.2mm gas gap GND 1.1mm Glass sheet Resistive paint -HV Mylar sheet Aluminum foil Charged particles ©Lei Xia, Argonne, LCWS05

Our starting point (2) : RPC signal: avalanche and streamer Gas mixture R134A:IsoButane:SF6 (Ar:R134A:Isobutane) Typical operating voltage: 7 – 10 KV Two types of signal Avalanche 2 – 10+ mV, without amplifier Fast rising time Signal width ~ 20ns Streamer > 100 mV, without amplifier Signal width 40 – 100+ ns Multiple (N) streamers per particle passing is normal N = 1 - 3 Avalanche signal No amplification Streamer signal No amplification ©Lei Xia, Argonne, LCWS05

Our starting point (3) RPC signal: efficiency Signal charge and efficiency is a function of operating voltage At low voltage: avalanche plateau (6.6 – 7.4 KV in plot) Almost pure avalanche signal Efficiency > 95% Streamer component < 3% Avalanche charge shows “threshold”, and a linear increase At higher voltage: streamer region Avalanche mode is our preferred running mode For a DHCAL, small signal pads (~ 1 x 1 cm2) are needed Digital readout Cross-talk / charge sharing between pads Noise rate ©Lei Xia, Argonne, LCWS05

The cold machine Little time between bunch crossing (300ns) Much time between trains (199ms) Data stored in RAM ASIC during train time Time between two trains: 200ms (5 Hz) Time between two bunch crossing: 337 ns Train length : 2820 bunch X (950 us)

Electronic requirements Simple analogue FE (Threshold detection) Multi-channel ASIC (64, 128, 256 ?) Channel by channel threshold tuning ? Multi-purpose preamp ? Avalanche Streamer GEMs Self-trigger Power pulsing (ASIC in the detector) Thickness constraint

DHCAL_TECH1 : Block scheme Very low counting rate Trigger on all channel OR (is there an optimum on the trigger) Low memory depht (how much low) Data internally saved during bunch train Data transfered to DAQ during inter-bunch 64 channels for multi-anode PM Close to MAROC chip

MAROC chip (Multi-Anode Read-Out Chip) Technology SiGe 0.35 m Chip area 12 mm2 power supply 3.3V Consumption 350 mW Pin count 228 pins Package CQFP240 Read out of PM64 64 inputs 64 trigger output 1 MUX charge output

4 discriminator thresholds MAROC block scheme Hold signal Photomultiplicator Photons Variable Gain Preamp. Slow Shaper S&H Bipolar Fast Shaper Unipolar 64 Tri g ger outputs Gain correction (6 bits) 4 discriminator thresholds (4*11bits DACs) Multiplexed charge output cmd_LUCID FS_choice LUCID

The analogue front-end A simple current conveyor (MAROC front-end) super common base architecture To ensure low input impedance To allow impedance tuning and avoid reflexions ? Measurement from OPERA-ROC FE ASIC

Physicist input needed ! RPC RPC measurement : What charge created when fired ? 0.1-5pC (D. Underwood LCWS2004) 3.4pC (V. Ammosov, LCWS2004) Rising time ? Falling time ? With what dispersion ? 2%/1m² (V. Ammosov, LCWS2004) Dark current (1µA/m² @ 9kV)? V. Ammosov, LCWS2004 Fancy effect ? Noise (0.5Hz/cm²)? V. Ammosov, LCWS2004 Trigger area : How many pixels per trigger ? 64, 128, 256 ? Optimisation with a simulation ?

Schedule Design & layout Foundry 1st proto Test on 1st prototype Today January 2006 April 2006 Summer 2006 Need to connect DHCAL_TECH1 to a RPC before any other iteration Need a strong interaction with RPC experts

Conclusion Work just begin on DHCAL front-end 2 weeks old Some ideas on front-end architecture Analogue blocks already exist Big work on digital block crucial interactions: With RPC experts for the front-end interface With DAQ experts for backend interface