Chapter 11 Instruction Sets Addressing Modes and Formats

10.1 Addressing Instructions is designed to be able to reference a large range of locations in main memory To achieve this objective, a variety of addressing techniques have been employed. Trade off between address range and/or the complexity of address calculation The addressing techniques are : Immediate, direct, indirect, register, register indirect, displacement, stack

Addressing Modes (a) Immediate LDA #100 (b) Direct LDA A Operand A Instruction Instruction Memory (a) Immediate LDA #100 Operand (b) Direct LDA A

Addressing Modes - continued.1 Ri Instruction Instruction Memory Registers R1 Operand (address) Ri Memory location Rn (c) Indirect LDA @A (d) Register MOV R1

Addressing Modes - continued.2 Op-code Ri Ri A Instruction Instruction Memory Memory Registers Registers R1 R1  Ri (base addr.) Operand Ri (address) Operand Rn Rn (e) Register Indirect LDA (R1) (f) Displacement LDA 100(R1)

Addressing Mode - continued.3 Instruction Implicit Top of Stack (g) Stack Stack addressing

Basic Addressing Modes EA = Effective Address A = content of the (an) address field in the instruction (X) = content of location X Principal Principal Mode Algorithm Advantage Disadvantage ------------------------------------------------------------------------------------------------- Immediate Operand = A No memory reference Limited opr. Magni. Direct EA = A Simple Limited addr. Space Indirect EA = (A) Large addr. Space Multiple mem. Ref. Register EA = R No mem. Reference Limited addr. Space Reg Indirect EA = (R) Large addr. Space Extra mem. Ref. Displacement EA = A + (R) Flexibility Complexity Stack EA = top of stack No mem. Reference Limited applicability

Addressing Mode Examples Immediate : ADD #100 ; add 100 to Accum. Direct: ADD A ; add content of addr. A to accumulator Indirect : ADD @A ; content of location A is address of operand. add content of loc. with that address to accum. Register Direct: ADD R1 ; add content of R1 to accumulator Reg. Indirect : ADD (R1) ; add content of mem. Location whose addr. is in R1 to acc.

Example - continued.1 Addressing with displacement is “rare”, but it may have an example like : ADD 1050(R1) where the base- address is the content of R1 and the displacement is 1050. In two address instruction, this may look like : ADD 1050(R1), (R2) where the base-address is in R1 and the displacement is 1050

Addressing Mode Examples - continued.1 Three common of displacement addressing : Relative addressing Base register addressing Indexing Relative addressing : Address of operand is the sum of address in the instruction plus the content of PC Op-code R1 Address of operand  PC Memory address

Addressing Mode Examples - continued.2 Base register addressing : Content of base-register is added to the operand address in the instruction Indexing : The address field of instruction, is added to content of index register to obtain the exact memory address (of the operand) The three address schemes we were just discussing, make use of a register to point to some specific segment of memory and uses the operand address in the instruction as the displacement

Pentium Addressing Modes Mode Algorithm Immediate Operand = A Register LA = R Displacement LA =(SR) + A Base LA = (SR) + (B) Base with Displacement LA = (SR) + (B) + A Scaled Index with Displacement LA = (SR) + (I)*S + A Base with Index and Displacement LA = (SR) + (B) + (I) + A Based w/ Scaled index & displacem. LA = (SR) + (I)*S +(B) +A Relative LA = (PC) + A --------------------------------------------------------------------------------------LA = Linear Address, (X) = Address of X, SR = Segment Register A = Content of address field in the instruction, B = Base register, I = Index Register, S = Scaling factor

10.2 Instruction Formats Format of instructions reflects the designer’s goal of the machine performance and flexibility Length of instruction varies, depending in the purpose. Most instructions chooses the length equal to the basic transfer information unit (word, 16 or 32 bits) Allocation of bits, usually depends on addressing modes it used. Register addressing for instance, takes less space than absolute addressing. Variable length instruction like Intel 8080 for instance, makes instruction fetch consumes another cycles Use fixed word instruction for faster fetch cycle

Program Example : unknown machine Memory Addressing addr. Label Operation or data info. ------------------------------------------------------------------------------------------ Assembler command SUM EQU 200 ORIGIN 201 N DATA 300 NUM1 DATA 301 ORIGIN 100 Statements that START MOVE R1,N generate machine MOVE R2,#NUM1 instructions CLR R0 LOOP ADD R0,(R2) INC R2 DEC R1 BGTZ LOOP MOVE SUM,R0 Assembler commands RETURN END START

Exercise Problems (1) Given the following values and a one-address machine with an accumulator,what values do the following instructions load into the accumulator? -Word 20 contains 40 -Word 40 contains 60 -Word 30 contains 50 -Word 50 contains 70 Load Immediate 20 (Load #20) Load Direct 20 (Load 20) Load Indirect 20 (Load @20) Load Direct 30 (Load 30) Load Indirect 30 (Load @30)

Exercise Problems (2) Given the following values and a one-address machine with an accumulator,what are the results of the following instructions? -Word 20 contains 40 -Word 40 contains 60 -Word 30 contains 50 -Word 50 contains 70 -R1 contains 40 -R2 contains 60 Load #20, then Store (R1) Load 20, then Add R2 Load 30, then Sub R1 Load @30, then Mul #2 Load 50, then Sub @40