Timer and Interrupts

clock (external or internal) General Purpose Timer The basic unit – counter (up or down) a clock source generate timing events (interrupts or timer output) if overflow or reach 0 if match with a preset value measure time – read counter values (captured) free running, reset or reload, compare clock (external or internal) 32 bit counter control circuit

input capture register Measurement Input-capture : identify the moment that an event occurs latch the counter value when triggered CPU can read the value later Output compare : control the timing of output bit CPU sets a value in output compare register compare with counter every clock cycle if equal, send an output signal External event counting Measuring elapsed time, pulse width, frequency, and period 32 bit counter input capture register clock load interrupt or ready flag event edge detection

Hardware Timer Typical approach – hardware unit generates an interrupt per unit of time (e.g. millisecond) Avoid overflow with a software counter (in memory) – incremented when interrupts assume the input clock of 2MHz (0.5x10-3 ms) set a compare counter to 1999 start counting with the input clock and, when equals to the compare register interrupt restart the counter from 0 interrupt or toggle output = 32 bit counter input clock (2MHz) restart compare register (1999)

DB-MX1: General Purpose Timer Maximum period of 512x65536 seconds at 32.768kHz or 436x65536 seconds at 38.4kHz 10ns resolution at 100MHz Programmable sources for the clock input, including external clock Input capture capability with programmable trigger edge Output compare with programmable mode Free-run and restart modes

GP Timer Module Registers Control register SW_reset, free-run/restart, capture edge, output mode, IRQ_en, clk_source, timer_en Counter, capture, compare registers Prescale register Status register (capture and compare events)

Waveform Generator Instead of interrupt, using a clock to generate a waveform To generate a square wave of 9600Hz, what value should be loaded into the comparator when the input clock is 10MHz? How to generate a waveform with a specific duty cycle 3 4 5 6 0 1 2 3 4 5 6 0 1 2 3 3 4 5 6 0 1 2 3 4 5 6 0 1 2 3

Pulse Width Measurement Capture counter values on edges Read the difference to know the width If the pulse is much longer, counter may overflow set value 0xFFFFFFF on compare register and use software counter to count number of overflows. start counting stop counting

Exceptions and Interrupts in ARM The processor is usually in user mode, and enters one of the exception modes when an unexpected event occurs. There are three different types of exceptions (some are called interrupts): - As a direct result of executing an instruction, such as: Software Interrupt Instruction (SWI) Undefined or illegal instruction Memory error during fetching an instruction As a side- effect of an instruction, such as: Memory fault during data read/ write from memory Arithmetic error (e. g. divide by zero) As a result of external hardware signals, such as: Reset Fast Interrupt (FIQ) Normal Interrupt (IRQ)

When an Exception Occurs ARM completes current instruction as best as it can, and departs from current instruction sequence to handle the exception by performing the following steps: - changes the operating mode corresponding to the particular exception. saves the current PC in the r14 corresponding to the new mode. For example, if FIQ occurs, the PC value is stored in r14( FIQ). saves the old value of CPSR in the Saved Processor Status Register of the new mode. disables exceptions of lower priority (to be considered later). forces the PC to a new value corresponding to the exception. This is effectively a forced jump to the Exception Handler or Interrupt Service Routine .

Exception Vector Address Each vector (except FIQ) is 4 bytes long (i. e. one instruction) You put a branch instruction at this address: B exception_ handler ; or LDR PC, IRQ_Addr FIQ is special in two ways: - the actual FIQ handler can be put at 0x0000001C onwards, because FIQ vector occupies the highest address FIQ has many more shadow registers. So you don’t have to save as many registers on the stack as other exceptions - faster.

Exception Return The handler program (or Interrupt Service Routine) must restore the user state exactly as it was before the exception occurred: Any modified user registers must be restored from the handler’s stack The CPSR must be restored from the appropriate SPSR PC must be changed back to the instruction address in the user instruction stream The return address was saved in r14 before entering the exception handler To return from a SWI or undefined instruction trap, use: MOVS pc, r14 To return from an IRQ, FIQ or prefetch abort, use: SUBS pc, r14, #4 To return from a data abort to retry the data access, use: SUBS pc, r14, #8 The ‘S’ modifier is NOT used to set the flags, but instead to restore the CPSR

Interrupts in Dragonball MX1 Interrupt sources  interrupt controller (AITC)  ARM core peripheral modules – timer, UART, etc. external interrupts forced interrupts (by software) AITC supports up to 64 interrupt sources maskable configurable (fast or normal) software controlled priority Low interrupt latency

ISR in Dragonball MX1 Vector table FUNCT vect_IRQ[64] = {norm_source00_isr, …., norm_source63_isr] ; void norm_scr00_isr(void) // norm_scr00_isr (0) { if((NIPNDL & 0x00000001) == 0) { } //verify interrupt source if(((NIPRIORITY0)&0xF)!=(NIVECSR&0xF)) { } //verify interrupt priority … } Set up IRQ handler read NIVECSR to determine the source of interrupt void __irq IRQ_Handler(void) short vectNum; vectNum = NIVECSR >> 16; // determine highest pending normal interrupt vect_IRQ[vectNum](); // find the pointer to correct ISR in the // look up table