M1.5 Foundation Tools Xilinx XC9500/XL CPLD

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Presentation transcript:

M1.5 Foundation Tools Xilinx XC9500/XL CPLD M1.5 Software/Fndtn

Agenda Program Manager Synthesis Implementation Fitting Report Timing Report

M1.5 Software Foundation provides simple interface from start to finish Integrated Project and Design Manager Full version and revision control Design entry Schematic VHDL Verilog ABEL FSM

Project Manager

Version Control (proj mgr)

Project Manager Allows for top level view of project Shows top level source Gives access to source hierarchy Push-button access to Design Entry tools Design Synthesis tools Design Implementation tools Download tools Simulation Tools

Project Manager Tabs give access to version and revision reports error messages

Basic Steps to Programmed Logic Start Project Manager Complete design entry Make certain that project contains top-level design Synthesize Simulate functional performance (suggested) Implement Simulate (Verify) timing and functionality (suggested) Program/Configure Device(s)

Basic Steps to Programmed Logic Start by clicking “START” -> “Programs” -> “Xilinx Foundation”-> “Xilinx Foundation Project Manager” (or the Foundation icon) Enter design HDL Finite State Machine Editor schematic Make certain that project contains all design files “Project” -> “Add Source Files” Specify Top-Level Design

Basic Steps to Programmed Logic Synthesize Simulate Functionality Implement

Basic Steps to Programmed Logic Simulate / Verify Timing Performance Program/Download

Steps to Programmed Logic Synthesize Design File Creates netlist from input file VHDL Verilog ABEL

Steps to Programmed Logic

Part Selector Choose device/family Run

Steps to Programmed Logic Implement Netlist Choose performance criteria (speed vs density) Enable “Produce Configuration Data” to create filename.jed for programming device Process Netlist and Fit to Architecture (Run)

Implementation Revision Options Run

Options Implementation options Target options (Produce Configuration Data for output file)

Implementation: Standard Options Allow for quick selection Optimize for: speed density

Implementation: Flow Engine

Steps to Programmed Logic Review fitter report file to verify fit and pin locations Here is an introduction to the reports

Reports Synthesis Implementation post-synthesis report optimized.chp netlist logfile netlist.log Implementation translation report project.bld fitter report project.rpt timing report project.tim

Implementation Reports Translation reports unused nets reports nets with no load or driver Fitter gives detailed information about the fitting and usage of CPLD device Timing gives detailed information about internal timing paths

Implementation Reports Read report by selecting “Report Browser”

Implementation Reports Yellow Sparkle indicates whether read

Design Example Sync DRAM controller Project included on lab disk as sdram1 File included on lab disk as sdramctl.vhd Report and timing files included Netlist file included

Fitting Report -Resources

Fitting Report- Resources (cont)

Fitting Report- FB Global

Timing Report (Summary)

Steps to Programmed Logic Program Device Connect download cable Invoke JTAG Programmer Establish Chain Program the device

JTAG Programmer

JTAG Programmer

Conclusion Foundation provides a simple and efficient method for taking a design from entry to programmed device. Synthesis allows for easy netlist generation. Implementation creates a file for programming the CPLD and provides in depth reports. JTAG Programmer provides a simple method for programming in system.