The Ohio State University CMS Muon System Electronics Replacements (DT Minicrate Upgrade & CSC Improvements) Ben Bylsma The Ohio State University 9 March, 2016 ACES 2016 – Fifth Common ATLAS CMS Electronics Workshop for LHC Upgrades

Muon System Electronics at HL-LHC Barrel Muon Drift Tubes (DT) HL-LHC Trigger Parameters HL-LHC/LHC L1A rate: 750 KHz 7.5X L1A Latency: 12.5 μsec 3.9X Luminosity: 0.75x1035 cm 10.4X (RUN 1) Replace on chamber electronics (Minicrate) Move trigger and readout complexity to USC (outside of radiation environment) 7.5X (LHC design) Endcap Muon Cathode Strip Chambers (CSC) Outer Chambers (ME1/2, 1/3, 2/2, 3/2, 4/2) Inner Chambers (ME1/1, 2/1, 3/1, 4/1) Replace Cathode Front-End Boards (CFEBs) to eliminate dependency on level 1 latency Replace DAQ readout electronics (DMB) to accommodate increased bandwidth 9 Mar 2016 ACES 2016, Ben Bylsma

CMS Drift Tube Electronics (Content provided by Sandro Ventura - INFN and Andrea Triossi - CERN) Original Minicrates Phase-2 Minicrates Highly integrated and complex system Many boards with various ASICs for specific tasks Trigger primitive generation performed on each chamber Filtered information sent to the counting room On-chamber electronics performs time digitization of all chamber signals Digital information sent through optical link to the counting room Complexity is brought into the counting room ... GBT FPGAs GBT link for data forwarding Radiation tolerant FPGAs which perform 1 ns time digitization (no filtering) Readout Time digitization Event matching Allows readout at 1 MHz Level 1 and 20 us latency Trigger primitive generation: maximum chamber resolution room for pt resolution increase Trigger segment finding, angle measurement=> single chamber trigger generation 9 Mar 2016 ACES 2016, Ben Bylsma

CMS Drift Tube Electronics –Stages to Phase 2 (Content provided by Sandro Ventura - INFN and Andrea Triossi - CERN) Before LS1: Separate Paths over copper to USC Read Out Server (ROS) and Trigger Sector Collector (TSC) electronics in UXC After LS1: ROS and TSC moved to USC Data converted and transmitted over fiber in UXC Data converted back to copper in USC Before LS2: ROS and TSC replaced with µTCA based electronics Higher performance to handle increased rates Optical decoupling facilitates electronics improvements without interfering with LHC schedule (optical splitting) 9 Mar 2016 ACES 2016, Ben Bylsma

CMS Drift Tube Electronics – Phase 2 Configuration (Content provided by Sandro Ventura - INFN and Andrea Triossi - CERN) Same analog Front End On-detector Minicrate electronics replaced (TDC) Single optical data path to USC (GBT links) Only optical PP and power supplies on tower (UXC) L1 trigger functionality moved to USC Backend is high performance FPGA based processors Merge DT-RPC-HO information (higher efficiency and rate reduction) A candidate for a demonstrator of a new backend is the TwinMux board The TwinMux is a µTCA board and is the platform for trigger processing in the post LS1 configuration 9 Mar 2016 ACES 2016, Ben Bylsma

Upgraded On-Detector Electronics Upgraded Back-End Electronics CMS Drift Tube Electronics – Phase 2 Details (Content provided by Sandro Ventura - INFN and Andrea Triossi - CERN) Upgraded On-Detector Electronics Minicrate function limited to time digitization and optical transmission Based on FPGAs (not ASICs) rad-tolerant, flexiblility Simple, robust system (fewer parts, less power) On Board Electronics for DT (OBEDT) module is simple Flash based FPGA implements Time-to-Digital- Converters (TDC), 1 ns resolution (chamber res. ~3ns) GBT chipset used to transmit data and control boards Performs slow control for FE access, monitoring, test pulses, and RPC connection Form factor similar to present (128 channels/board) R&D in progress Upgraded Back-End Electronics FPGA based processors in USC will generate trigger primitives and perform readout functionalities Possible performance improvements: Better time resolution (12.5ns -> ~3ns) improves position, angle, and Pt resolution, better Bx ID Reduced deadtime (400ns -> ~100ns) reduce loss of hits masked by background Superlayer granularity not limited to groups of 9 cells implies fewer ghosts and better Bx ID Improved θ resolution (32cm -> ~1mm), better matching with tracker information Triggers not limited to two per chamber Trigger primitive generation will utilize all SuperLayers in the chamber and maybe neighboring chambers as well Combine RPC and HO hits with DT segments improves efficiency and reduces rates Study for a new trigger algorithm on raw TDC data has started 9 Mar 2016 ACES 2016, Ben Bylsma

CMS Drift Tube Electronics – Summary Minicrate electronics simplified to one board type for TDC implementation and I/O over GBT links Relocating Sector Collector to USC allows for improvements in DT trigger and readout Merged DT-RPC-HO information leads to higher efficiency, reduced rate Readout bandwidth increased 9 Mar 2016 ACES 2016, Ben Bylsma

CMS Cathode Strip Chamber (CSC) Electronics At HL-LHC Rates HL-LHC Trigger Parameters HL-LHC/LHC L1A rate: 750 KHz 7.5X L1A Latency: 12.5 μsec 3.9X Luminosity: 0.75x1035 cm 10.4X (7.5X) Cathode Front-End Boards (CFEBs) 16 channels/layer with 6 layers SCA analog storage (96 caps/channel) Requires low latency pre-trigger Capacity of 5 events at most 1 ADC/layer (16 channels multiplexed) ~26usec to digitize and readout 1 event Note: At present L1A rate and L1A latency CFEBs are fine at HL-LHC luminosity SCA’s hit with 30X (L1A Rate + Latency) Overflow Fraction of Event Loss – No precision Data (ADC,timing) recorded from Cathodes We need to replace CFEBs on ME2/1, ME3/1, and ME4/1 Already replaced ME1/1 (in LS1) Not Conservative: Requires two modifications of CFEB/DMB firmware. Best we will be able to do. 9 Mar 2016 ACES 2016, Ben Bylsma

CMS CSC Electronics - Replace CFEBs With Digital CFEBs (DCFEB) DCFEB Basic Block Diagram Flash ADC + digital pipeline replaces analog SCA storage Continuously digitizing all channels Effectively no dead-time No L1A latency dependence (deep pipeline) Optical fiber output for trigger and DAQ (Line rate 3.2 Gbps) (Data rate 2.5 Gbps) pre ADC + - ref 16 FPGA 8 pairs . 6 layers Serial Opt. Trnscvr To DMB over Fiber 1 – 2.5Gbps GTX 8 16 pairs Pipeline/FIFOs Serial LVDS 8 Triad signals comp 48 To TMB over Skewclear ~2.56Gbps DCFEBs already in use during run 2 on ME1/1 Replacing CFEBs with DCFEBs on ME2/1, ME3/1, and ME4/1 requires 540 new DCFEBs (compare to 504 needed on ME1/1) Represents 25% of all CFEBs 90% of rate will be through DCFEBs 9 Mar 2016 ACES 2016, Ben Bylsma

CMS CSC Electronics - Trigger, DAQ, and FED (Data Bandwidth) Increased luminosity at HL-LHC implies: Increased data bandwidth requirements Replacement of CFEBs with DCFEB Implies: Low Voltage Distribution Board (LVDB) -> LVDB5 Trigger MotherBoard (TMB) -> Optical TMB (OTMB) DAQ MotherBoard (DMB) -> Optical DMB (ODMB) Data Rates at 0.75x1035cm-2s-1 At present DMB -> DDU links are 1.28 Gbps ME1/1 ODMBs need to be replaced with high bandwidth version of ODMB (72 needed) ME2/1, 3/1, 4/1 DMBs need to be replaced with new ODMB2s (108 needed) ME2/1, 3/1, 4/1 TMBs need to be replaced with OTMBs No changes needed; simply produce more (108 needed) ME2/1, 3/1, 4/1 LVDBs need to be replaced with LVDB5s Major changes needed in the FED design 9 Mar 2016 ACES 2016, Ben Bylsma

ODMB -> increased bandwidth ODMB CMS CSC Electronics – Optical DAQ Mother Board (ODMB) (Content provided by Manuel Franco Sevilla - UCSB) ME1/1 ODMB -> increased bandwidth ODMB 1.6 Gbps to 2X 12.5+ Gbps (line rates) Control signals for 7 DCFEBs ME234/1 DMB -> ODMB 1.6 Gbps to 12.5+ Gbps (line rates) Control signals for 5 DCFEBs Main difference is front panel interface 9 Mar 2016 ACES 2016, Ben Bylsma

360 DMBs with 1.6 Gbps optical links (from ME1/2, 1/3, 2/2, 3/2, 4/2) CMS CSC Electronics – Back End FED Crate in USC (Content provided by Jason Gilmore - TAMU) End cap muon FED system receives data from a mixed system of DAQ boards 360 DMBs with 1.6 Gbps optical links (from ME1/2, 1/3, 2/2, 3/2, 4/2) 72 ODMBs with 2 X 12.5 Gbps optical links (from ME1/1) 108 ODMBs with 12.5 Gbps optical links (from ME2/1, 3/1, 4/1) FPGA based processor boards, probably µTCA or ATCA form factor (common CMS solution?) Currently available possibilities are MP7, CTP7, and MTF7 (all Virtex 7) 17 fiber links per Trigger Sector (TS) 3 TS/processor implies 12 processors needed R&D can proceed with current technology Technology decision can be delayed until 2022 MP7 CTP7 MTF7 9 Mar 2016 ACES 2016, Ben Bylsma

CMS CSC Electronics – Possible Timeline of CSC Upgrade On-Chamber electronics install during LS2 Install off-chamber electronics (ODMBs, and FED) during LS3 Requires running with a mixed system during Run3 (DMBs reading out DCFEBs) DCFEBs maintain a copper data path to DMBs Requires firmware changes on DMB Changes have been made and tested at test stands 9 Mar 2016 ACES 2016, Ben Bylsma

CMS CSC Electronics – Summary of CSC Upgrade Expected trigger and data rates at HL-LHC will cause substantial data loses in the current electronics for ME1/1, 2/1, 3/1, and 4/1 On chamber upgrade to DCFEBs provides no dead-time and deep pipelines to accommodate long trigger latencies Off chamber electronics upgrade provides higher bandwidth DAQ DCFEB, OTMB, and LVDB designs are ready for production now and have been proven in Run2 ODMB and FED designs will benefit by waiting several years 9 Mar 2016 ACES 2016, Ben Bylsma